Agilex™ 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide

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ID 776646
Date 11/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Intel® SoC EDS 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board System MAX® 10 with Default Factory Image 3.3.2. Restoring Board QSPI Flash with the Default Factory Image
4. Board Test System x
4.1. Setting Up the BTS GUI Running Environment 4.2. BTS Functionalities 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. Identify Test Pass or Fail-based on BTS GUI Test Status
4.1. Setting Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. BTS Functionalities x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The FMCA NRZ Tab 4.2.5.3. The FMCB NRZ Tab 4.2.5.4. The QSFPDD400/QSFPDD800 PAM4 Tab 4.2.5.5. The QSFP NRZ Tab 4.2.5.6. The SFP Tab 4.2.5.7. The OSFP Tab
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode) 5.2. Configuring the FPGA Device by Avalon® Streaming Modes
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Board Overview and Components A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Memory Interfaces A.7. Communication Interfaces A.8. Daughter Cards
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

B. Developer Resources

Use the following links to check the Intel® website for other related information.
Table 25.   Agilex™ 7 FPGA I-Series Transceiver Development Kit References
Reference Description
Agilex™ 7 FPGA I-Series Transceiver Development Kit page Latest board design files, reference designs, and kit installation for Windows* and Linux*.
Rocketboard.org Open-source community website supporting SoC development including Altera and Partner SoC development kit targets and related designs and documentation.
Intel® SoC FPGA Embedded Development Suite (SoC EDS) User Guide Installing the SoC EDS and ARM DS-5. Preloader user guide. Hard Processor System (HPS) Flash programmer. Bare Metal and Linux* compilers. Debugging.
Agilex™ 7 FPGA Board Design Guided Journey The interactive FPGA Board Guided Journey provides step-by-step guidance for developing printed circuit boards (PCBs) using Agilex™ 7 devices.
Agilex™ 7 Device Design Guidelines Guidelines, recommendations, and a list of factors to consider for designs that use the Agilex™ 7 SoC devices.
AN 958: Board Design Guidelines Board design-related resources for Altera®  devices. Its goal is to help you implement successful high-speed PCBs that integrate device(s) and other elements.
Agilex™ 7 Power Management User Guide Describes the Agilex™ 7 devices power-optimization features, power-up and power-down sequences, power distribution network, voltage and temperature monitoring systems with a design example to read the TSDs, and power optimization techniques.
Agilex™ 7 Power Distribution Network Design Guidelines Provides information for the Agilex™ 7 device family power distribution network (PDN) design guidelines.
FPGA SmartVID SmartVID is a feature on select Altera® FPGAs where the device identifies the optimal voltage that it should be operated at, and provides this information to the power regulator via the PMBus. The term represents Smart Voltage IDentification (SmartVID).
SmartVID Debug Checklist and Voltage Regulator Guidelines Provides the checklist to assist you to rule out the possible causes of configuration failure due to SmartVID.
Agilex™ 7 Configuration User Guide Provides the configuration process, the device pins required for configuration, the available configuration schemes, remote system updates, and debugging. This user guide also provides an overview of the secure device manager (SDM) which manages security for the configuration bitstream.
Documentation: Agilex™ 7 Agilex™ 7 device documentation.
Cadence* Capture CIS Schematic Symbols Agilex™ 7 OrCAD symbols.
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