Agilex™ 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide

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ID 776646
Date 11/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Intel® SoC EDS 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board System MAX® 10 with Default Factory Image 3.3.2. Restoring Board QSPI Flash with the Default Factory Image
4. Board Test System x
4.1. Setting Up the BTS GUI Running Environment 4.2. BTS Functionalities 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. Identify Test Pass or Fail-based on BTS GUI Test Status
4.1. Setting Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. BTS Functionalities x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The FMCA NRZ Tab 4.2.5.3. The FMCB NRZ Tab 4.2.5.4. The QSFPDD400/QSFPDD800 PAM4 Tab 4.2.5.5. The QSFP NRZ Tab 4.2.5.6. The SFP Tab 4.2.5.7. The OSFP Tab
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode) 5.2. Configuring the FPGA Device by Avalon® Streaming Modes
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Board Overview and Components A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Memory Interfaces A.7. Communication Interfaces A.8. Daughter Cards
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

1.2. Feature Summary

  • Agilex™ 7 I-Series FPGA, 4047 KLE, 3948A package
  • F-Tile 1 (12A):
    • 16 FGT transceiver channels fan out to FPGA Mezzanine Card Plus (FMC+) connector
  • F-Tile 2 (12B):
    • 4 FHT transceiver channels fan out to Quad Small Form Factor Pluggable Double Density 800 (QSFP-DD800) connector
    • 8 FGT transceiver channels to Quad Small Form Factor Pluggable Double Density (QSFP-DD) connector
    • 4 FGT Transceiver channels to Quad Small Form Factor Pluggable (QSFP) connector
  • F-Tile 3 (12C):
    • 4 FHT transceiver channels fan out to QSFP-DD800 connector
    • 8 FGT transceiver channels to QSFP-DD connector
    • 4 FGT Transceiver channel to Small Form Factor (SFF) connector
    • 4 FGT transceiver to channels to QSFP connector
  • F-Tile 4 (13A):
    • 4 FGT Transceiver to channels to QSFP connector
    • 8 FGT transceiver channels to QSFP-DD connector
  • F-Tile 5 (13B):
    • 4 FGT Transceiver to channels to Mini Cool Edge IO (MCIO)
    • 8 FGT transceiver channels to QSFP-DD connector
    • 4 FHT transceiver channels fan out to Octal Small Form Factor Pluggable (OSFP) connector
  • F-Tile 6 (13C):
    • 16 FGT channels to FMC+
    • 4 FHT transceiver channels fan out to OSFP connector
  • SR DDR4 2666 MT/s (× 72 w/ECC), 16 GB.
  • SR DDR4 2666 MT/s (× 72 w/ECC), 16 GB 1 DPC Dual In-line Memory Modules (DIMM) connector
Note: QSFP-DD400 and OSFP work up to 400 Gbps (50G x 8) PAM4 in DK-SI-AGI040FES. QSFP-DD800 and OSFP work up to 800 Gbps (100G x 8) PAM4 in DK-SI-AGI040EA.
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