Agilex™ 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide

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ID 776646
Date 11/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Intel® SoC EDS 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board System MAX® 10 with Default Factory Image 3.3.2. Restoring Board QSPI Flash with the Default Factory Image
4. Board Test System x
4.1. Setting Up the BTS GUI Running Environment 4.2. BTS Functionalities 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. Identify Test Pass or Fail-based on BTS GUI Test Status
4.1. Setting Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. BTS Functionalities x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The FMCA NRZ Tab 4.2.5.3. The FMCB NRZ Tab 4.2.5.4. The QSFPDD400/QSFPDD800 PAM4 Tab 4.2.5.5. The QSFP NRZ Tab 4.2.5.6. The SFP Tab 4.2.5.7. The OSFP Tab
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode) 5.2. Configuring the FPGA Device by Avalon® Streaming Modes
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Board Overview and Components A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Memory Interfaces A.7. Communication Interfaces A.8. Daughter Cards
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.2. System Management

Two MAX® 10 FPGAs (10M16SCU324C8G) are used for system management. System MAX® 10 acts as system controller. It handles FPGA AvST configuration, I2C bus access, fan speed control and system reset functions. The UB2/PWR MAX® 10 acts as Power manager and on-board JTAG controller. Refer to below description for each function:

  • Power management: Control systems and FPGA power up and optional down sequence, supervise power regulators/switches status and manage power faults, supervise temperature sensor interrupt signals and manage temperature faults.
  • JTAG controller: Manage JTAG chain topology, JTAG master source and JTAG slaves by S19.
Table 7.  JTAG Master Sources
Schematic Signal Name Description
EXT_JTAG_TCK/TDO/TMS/TDI JTAG header J11 for Intel® FPGA Download Cable
FX2_Dp/n Input port J10 for on-board Intel download circuit
Mode S20[4:1]

S19 [4][3] [2] [1]

On: bypass from chain

Off: enable in chain

 Function
000

ON/ON/ON

(Default)

S19.1 (SDM+HPS)

S19.2 (SysMax)

S19.3(FMC_B)

S19.4 (FMC_A)

Mode 1: On-board Intel download circuit act as the only JTAG Master.

Chained HPS with SDM nodes internally.

Mode 3: External Intel® FPGA Download Cable act as the only JTAG Master.

Chained HPS with SDM nodes internally.
001 ON/ON/OFF

SDM is always enabled in the JTAG chain

S19.1 (HPS)

S19.2 (SysMax)

S19.3(FMC_B)

S19.4 (FMC_A)

Mode 2: On-board Intel download circuit act as the only JTAG Master.

Chained HPS with SDM nodes externally.

Mode 4: External Intel® FPGA Download Cable act as the only JTAG Master.

Chained HPS with SDM node externally.
010 ON/OFF/ON

S19.1 (SDM+HPS)

S19.2 (SysMax)

S19.3 (FMC_B)

Mode 5: FMC_A acts as the only JTAG Master.

Chained HPS with SDM nodes internally.

011 ON/OFF/OFF

SDM is always enabled in the JTAG chain

S19.1 (HPS)

S19.2 (SysMax)

S19.3(FMC_B)

Mode 6: FMC_A acts as the only JTAG Master.

Chained HPS with SDM nodes externally.
100 OFF/ON/ON

S19.1 (SDM)

S19.2 (SysMax)

S19.3(FMC_B)

S19.4 (FMC_A)

Mode 7: Both On-board Intel download circuit and OOBE act as JTAG Masters.

Separated HPS and SDM JTAG chains, OOBE only drive HPS

Mode 8: Both External Intel® FPGA Download Cable and OOBE JTAG act as JTAG Masters.

Separated HPS and SDM JTAG chains, OOBE only drive HPS
101 OFF/ON/OFF

S19.1 (SDM)

S19.2 (SysMax)

S19.3(FMC_B)

Mode 9: Both On-board Intel download circuit and FMC_A act as JTAG Masters.

Separated HPS and SDM JTAG chains, FMC only drive HPS

Mode 10: Both External Intel® FPGA Download Cable and FMC_A act as JTAG Masters.

Separated HPS and SDM JTAG chains, FMC only drive HPS
110 OFF/OFF/ON N/A

Mode 11: Both On-board Intel download circuit and OOBE act as JTAG Masters.

On-board Intel download circuit only drive SDM, OOBE only drive HPS.

111 OFF/OFF/OFF N/A

Mode 12: Both On-board Intel download circuit and FMC_A act as JTAG Masters.

On-board Intel download circuit only drive SDM, FMC only drive HPS.

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