Agilex™ 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide

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ID 776646
Date 11/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Intel® SoC EDS 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board System MAX® 10 with Default Factory Image 3.3.2. Restoring Board QSPI Flash with the Default Factory Image
4. Board Test System x
4.1. Setting Up the BTS GUI Running Environment 4.2. BTS Functionalities 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. Identify Test Pass or Fail-based on BTS GUI Test Status
4.1. Setting Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. BTS Functionalities x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The FMCA NRZ Tab 4.2.5.3. The FMCB NRZ Tab 4.2.5.4. The QSFPDD400/QSFPDD800 PAM4 Tab 4.2.5.5. The QSFP NRZ Tab 4.2.5.6. The SFP Tab 4.2.5.7. The OSFP Tab
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode) 5.2. Configuring the FPGA Device by Avalon® Streaming Modes
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Board Overview and Components A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Memory Interfaces A.7. Communication Interfaces A.8. Daughter Cards
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide

Document Version Changes
2024.11.21
  • Updated the Overview chapter:
    • Updated Table: Ordering Information:
      • Replaced the device part number for the Agilex™ 7 FPGA I-Series Transceiver Development Kit (Production1 6 × F-Tile) in Table: Ordering Information from "AGIC040R39A1E1VB" to "AGIC040R39A1E1VC".
      • Updated the serial number identifiers for the production and ES1 development kits.
    • Added new Figure: Agilex™ 7 FPGA I-Series Transceiver Development Kit—Top View.
    • Updated Figure: Agilex™ 7 FPGA I-Series Transceiver Development Kit—Block Diagram.
    • Updated Feature Summary.
    • Updated Recommended Operating Conditions.
  • Updated the Getting Started chapter:
    • Added new topics:
      • Before You Begin
      • Handling the Board
      • Installing the Quartus® Prime Pro Edition Software
      • Installing the Intel® SoC EDS
      • Installing the Development Kit
      • Installing the Intel® FPGA Download Cable II Driver
    • Removed the following topics:
      • Quick Start Guide
      • Design Examples
  • Updated and retitled chapter Power Up the Development Kit to Development Kit Setup.
    • Retitled topic Power Up to Powering Up the Development Kit.
    • Retitled topic Perform Board Restore to Performing Board Restore.
    • Retitled topic Restore board System Intel® MAX® 10 with default factory image to Restoring Board System Intel® 10 with Default Factory Image.
    • Retitled topic Restore Board QSPI Flash with the Default Factory Image to Restoring Board QSPI Flash with the Default Factory Image.
  • Updated the Board Test System chapter:
    • Updated and retitled topic Installing Quartus® Prime Software to Setting Up the Quartus® Prime Software for BTS Operation.
    • Updated all the figures in the BTS Functionalities chapter.
    • Retitled topic Test the Functionality of the Development Kit to BTS Functionalities.
    • Retitled topic The QSFPDD400 PAM4 Tab to The QSFPDD400/QSFPDD800 PAM4 Tab.
  • Updated the Development Kit Hardware and Configuration chapter:
    • Retitled topic Configure the FPGA Device by Active Serial (AS) Modes (Default Mode) to Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode).
    • Retitled topic Configure the FPGA Device by Avalon-ST (AvST) Modes to Configuring the FPGA Device by Avalon Streaming Modes.
  • Retitled appendix chapter Additional Information to Safety and Regulatory Compliance Information.
  • Restructured the document to improve clarity and for ease of reference.
  • Updated the document for the latest branding standards.
2023.05.31 Initial release.
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