Agilex™ 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide

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ID 776646
Date 11/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Intel® SoC EDS 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board System MAX® 10 with Default Factory Image 3.3.2. Restoring Board QSPI Flash with the Default Factory Image
4. Board Test System x
4.1. Setting Up the BTS GUI Running Environment 4.2. BTS Functionalities 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. Identify Test Pass or Fail-based on BTS GUI Test Status
4.1. Setting Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. BTS Functionalities x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The FMCA NRZ Tab 4.2.5.3. The FMCB NRZ Tab 4.2.5.4. The QSFPDD400/QSFPDD800 PAM4 Tab 4.2.5.5. The QSFP NRZ Tab 4.2.5.6. The SFP Tab 4.2.5.7. The OSFP Tab
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode) 5.2. Configuring the FPGA Device by Avalon® Streaming Modes
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Board Overview and Components A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Memory Interfaces A.7. Communication Interfaces A.8. Daughter Cards
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.7. Communication Interfaces

MCIO Port (J37)

The MCIO slot is a PCIe* 4.0 x4 port which fans out from Agilex™ 7 I-Series FPGA F-Tile. This port is designed to meet the standard MCIO pinout.

System MAX® 10 acts as the board management controller (BMC) of the development kit. It manages power up reset for both PCIe* root port and PCIe* end point. PCIE_1_PERSTn_A signal acts as output and input respectively.

Table 12.  MCIO Port
Schematic Signal Name Description
PCIE_1_PERSTn_A PCIe* endpoint/rootport reset
PCIE_1_ALERTn_A PCIe* Alert
PCIE_100M_REF_AP/AN PCIe* reference clock
PCIE_1_SCL_A/SDA_A PCIe* I2C bus
PCIE_1_TX_[0:3]_DP/DN Transceiver TX
PCIE_1_RX_[0:3]_DP/DN Transceiver RX

QSFPDD

Agilex™ 7 FPGA I-Series Transceiver Development Kit supports 4x QSFPDD ports. The QSFPDD port fans out from the Agilex™ 7 I-Series FPGA F-Tile (FGT). All 8 channels per QSFPDD can run up to 25 Gbps NRZ and 50 Gbps PAM4.

Table 13.  QSFPDD Connector -0 (12B/J27)
Schematic Signal Names Description
QSFPDD0_MODPRS_L Module present
QSFPDD0_RESET_L Module reset
QSFPDD0_MODSEL_L Mode select
QSFPDD0_LPMODE Initial mode
QSFPDD0_INT_L Interrupt
I2C_QSFP_1_SCL I2C clock
I2C_QSFP_1_SDA I2C data
QSFPDD0_TX_[0:7]_DP/DN Transceiver TX
QSFPDD0_RX_[0:7]_DP/DN Transceiver RX
Table 14.  QSFPDD Connector 1 (12C/J48)
Schematic Signal Names Description
QSFPDD1_MODPRS_L Module present
QSFPDD1_RESET_L Module reset
QSFPDD1_MODSEL_L Mode select
QSFPDD1_LPMODE Initial mode
QSFPDD1_INT_L Interrupt
I2C_QSFP_3_SCL I2C clock
I2C_QSFP_3_SDA I2C data
QSFPDD1_TX_[0:7]_DP/DN Transceiver TX
QSFPDD1_TX_[0:7]_DP/DN Transceiver RX
Table 15.  QSFPDD Connector -2 (13A/J69)
Schematic Signal Names Description
QSFPDD2_MODPRS_L Module present
QSFPDD2_RESET_L Module reset
QSFPDD2_MODSEL_L Mode select
QSFPDD2_LPMODE Initial mode
QSFPDD2_INT_L Interrupt
I2C_QSFP_2_SCL I2C clock
I2C_QSFP_2_SDA I2C data
QSFPDD2_TX_[0:7]_DP/DN Transceiver TX
QSFPDD2_RX_[0:7]_DP/DN Transceiver RX
Table 16.  QSFPDD Connector -3 (13B/J67)
Schematic Signal Names Description
QSFPDD3_3V3_MODPRS_L Module present
QSFPDD3_3V3_RESET_L Module reset
QSFPDD3_3V3_MODSEL_L Mode select
QSFPDD3_3V3_LPMODE Initial mode
QSFPDD3_3V3_INT_L Interrupt
I2C_QSFP_2_SCL I2C clock
I2C_QSFP_2_SDA I2C data
QSFPDD3_TX_[0:7]_DP/DN Transceiver TX
QSFPDD3_RX_[0:7]_DP/DN Transceiver RX

QSFPDD800

Agilex™ 7 FPGA I-Series Transceiver Development Kit supports 1x QSFPDD800 port. QSFPDD800 port fans out from the Agilex™ 7 I-Series FPGA F-Tile (FHT). The FHT Tile from bank 12B and 12C can run up to 400 Gbps (50G x 8) PAM4 in DK-SI-AGI040FES. 4 FHT lanes from bank 12B+4 FHT lanes from bank 12C are terminated directly to QSFPDD800 connector lanes [0:7] (J22).

Note: QSFPDD800 works up to 800 Gbps (100 G x 8) PAM4 in DK-SI-AGI040EA.
Table 17.  QSFPDD800 (12B+12C)
Schematic Signal Names Description
QSFPDD800_MODPRS_L Module present
QSFPDD800_RESET_L Module reset
QSFPDD800_MODSEL_L Mode select
QSFPDD800_LPMODE Initial mode
QSFPDD800_INT_L Interrupt
I2C_QSFP_1_SCL I2C clock
I2C_QSFP_1_SDA I2C data
QSFPDD800_TX_[0:7]_DP/DN Transceiver TX
QSFPDD800_RX_[0:7]_DP/DN Transceiver RX

QSFP

Agilex™ 7 FPGA I-Series Transceiver Development Kit supports 3x QSFP ports. The QSFP port fans out from the Agilex™ 7 I-Series FPGA F-Tile (FGT). All 4 channels can run up to 1 Gbps per lane.

Table 18.  QSFP Connector-0 (12B/J57)
Schematic Signal Names Description
QSFP0_MOD_PRS_N Module present
QSFP0_RST Module reset
QSFP0_MOD_SEL_L Mode select
QSFP0_LP_MODE Initial mode
QSFP0_INTERRUPT_N Interrupt
I2C_QSFP_1_SCL I2C clock
I2C_QSFP_1_SDA I2C data
QSFP0_TX_[0:3]_DP/DN Transceiver TX
QSFP0_RX_[0:3]_DP/DN Transceiver RX
Table 19.  QSFP Connector-1 (12C/J58)
Schematic Signal Names Description
QSFP1_MOD_PRS_N Module present
QSFP1_RST Module reset
QSFP1_MOD_SEL_L Mode select
QSFP1_LP_MODE Initial mode
QSFP1_INTERRUPT_N Interrupt
I2C_QSFP_3_SCL I2C clock
I2C_QSFP_3_SDA I2C data
QSFP1_TX_[0:3]_DP/DN Transceiver TX
QSFP1_RX_[0:3]_DP/DN Transceiver RX
Table 20.  QSFP Connector-2 (13A/J66)
Schematic Signal Names Description
QSFP2_MOD_PRS_N Module present
QSFP2_RST Module reset
QSFP2_MOD_SEL_L Mode select
QSFP2_LP_MODE Initial mode
QSFP2_INTERRUPT_N Interrupt
I2C_QSFP_2_SCL I2C clock
I2C_QSFP_2_SDA I2C data
QSFP2_TX_[0:3]_DP/DN Transceiver TX
QSFP2_RX_[0:3]_DP/DN Transceiver RX

OSFP

Agilex™ 7 FPGA I-Series Transceiver Development Kit supports OSFP ports. OSFP port fans out from the Agilex™ 7 I-Series FPGA F-Tile (FHT). The FHT Tile from bank 13B and 13C can run up to 400 Gbps (50G x 8) PAM4 in DK-SI-AGI040FES. 4 FHT lanes from bank 13B + 4 FHT lanes from bank 13C are terminated directly to OSFP connector lanes [0:7] (J45).

Note: OSFP works up to 800 Gbps (100G x 8) PAM4 in DK-SI-AGI040EA.
Table 21.  OSFP (13B+13C)
Schematic Signal Names Description
OSFP_LPW_PRSNT_N Initial mode/Module Present
OSFP_INT_RST_N Interrupt/Reset
I2C_OSFP_3V3_SCL I2C clock
I2C_OSFP_3V3_SDA I2C data
OSFP_TX[0:7]_DP/DN Transceiver TX
OSFP_RX[0:7]_DP/DN Transceiver RX

SFP

Agilex™ 7 FPGA I-Series Transceiver Development Kit supports 4x SFP ports. SFP port fans out from the Agilex™ 7 I-Series FPGA F-Tile (FGT). All 4 channels can run up to 1 Gbps/each SFP channel.

Table 22.  SFP (12C/J77)
Schematic Signal Names Description
SFP3_TX_DISABLE Transmitter Disable
SFP3_RATE_SEL Module Rate Select 0
SFP3_MOD0_PRSNT_N Module Present
SFP3_LOS Loss of Signal
SFP3_TX_FAULT Transmitter Fault Indication
SFP3_RS1 Module rate select 1
SFP3_MOD0_SCL I2C clock
SFP3_MOD0_SDA I2C data
SFP3_TX_DP/DN Transceiver TX
SFP3_RX_DP/DN Transceiver RX
SFP2_TX_DISABLE Transmitter Disable
SFP2_RATE_SEL Module Rate Select 0
SFP2_MOD1_PRSNT_N Module Present
SFP2_LOS Loss of Signal
SFP2_TX_FAULT Transmitter Fault Indication
SFP2_RS1 Module rate select 1
SFP2_MOD1_SCL I2C clock
SFP2_MOD1_SDA I2C data
SFP2_TX_DP/DN Transceiver TX
SFP2_RX_DP/DN Transceiver RX
SFP1_TX_DISABLE Transmitter Disable
SFP1_RATE_SEL Module Rate Select 0
SFP1_MOD2_PRSNT_N Module Present
SFP1_LOS Loss of Signal
SFP1_TX_FAULT Transmitter Fault Indication
SFP1_RS1 Module rate select 1
SFP1_MOD2_SCL I2C clock
SFP1_MOD2_SDA I2C data
SFP1_TX_DP/DN Transceiver TX
SFP1_RX_DP/DN Transceiver RX
SFP0_TX_DISABLE Transmitter Disable
SFP0_RATE_SEL Module Rate Select 0
SFP0_MOD3_PRSNT_N Module Present
SFP0_LOS Loss of Signal
SFP0_TX_FAULT Transmitter Fault Indication
SFP0_RS1 Module rate select 1
SFP0_MOD3_SCL I2C clock
SFP0_MOD3_SDA I2C data
SFP0_TX_DP/DN Transceiver TX
SFP0_RX_DP/DN Transceiver RX

FMC + Connectors

Agilex™ 7 FPGA I-Series Transceiver Development Kit supports 2x FMC+ slots for functional expandability. The x16 FGT lanes from bank 13C and 12A are terminated to FMC-A (J7) and FMC-B (J9) connectors respectively. Auxiliary signals are controlled by the System MAX® 10.

Serial Buses

SDM I/Os (SDM_IO0/12) and MAX® 10 I/Os (VCCL_SDA/SCL) share the same I2C bus which talks with Agilex™ 7 FPGA core regulators. By default, SDM acts as SmartVID master and system MAX® 10 act as Power GUI master in this chain.

System MAX® 10 I/Os (PMB_SDA/SCL) manages the second I2C bus which access all I2C slave regulators, except Agilex™ 7 FPGA core regulators.

System MAX® 10 supports I2C master dedicated to clock related devices (CLK_I2C_SDA/SCL), which manages 4# clock devices and SPI from Agilex™ 7 could control SI5518 (clock device).

Agilex™ 7/System MAX® 10 also manages QSFPDD800, 4x QSFPDD, 1DPC DIMM, 3x QSFP, SFP, OSFP, 2x FMC, MCIO I2C buses System MAX® 10 supports as a I2C Master for Current (IVSNS_I2C_SDA /SCL) and Temperature sensors (T_SNS_SCL/SDA).

The SGPI Interface exists between System MAX® 10 and Agilex™ 7 (FPGA_SGPIO_SYNC/FPGA_SGPO/FPGA_SGPIO_CLK/FPGA_SGPI).

System MAX® 10 as SPI Master to communicate with Agilex™ 7 (MAX10_SPI_SCLK/CSN/MOSI/MISO).

Agilex™ 7 as SPI Master to communicate with System MAX® 10 (FPGA_SPI_SCLK/CSN/MOSI/MISO).

Table 23.  I2C Debug Headers
Schematic Signal Name Description
PMB_SCL/SDA VRs I2C header J41
CLK_I2C_SDA/SCL_3V3 System MAX® 10 Clock I2C bus header J140 (ES board) or J42 (production board)
IVSNS_I2C_SDA /SCL Current sensor J149
T_SNS_SCL/SDA Temperature sensor I2C J79
Table 24.  SPI Headers
Schematic Signal Name Description

SI5518_I2C_SCL_SCLK/SI5518_GPIO3_SDO/

SI5518_I2C_SDA_SDIO/SI5518_A0_CSB

 SI5518 SPI Header J31
Figure 34. I2C Serial Bus
Level Two Title