Intel Agilex® 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide

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ID 776646
Date 5/31/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Power Up the Development Kit 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Revision History A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Intel® Quartus® Prime Software and Driver Installation 2.2. Quick Start Guide 2.3. Design Examples
3. Power Up the Development Kit x
3.1. Default Settings 3.2. Power Up 3.3. Perform Board Restore
3.3. Perform Board Restore x
3.3.1. Restore board System Intel® MAX® 10 with default factory image 3.3.2. Restore Board QSPI Flash with the Default Factory Image
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. Identify Test Pass or Fail-based on BTS GUI Test Status
4.1. Set Up BTS GUI Running Environment x
4.1.1. Download OpenJDK 4.1.2. Download OpenJFX 4.1.3. Install OpenJDK and OpenJFX 4.1.4. Install Intel® Quartus® Prime Software 4.1.5. Run BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The FMCA NRZ Tab 4.2.5.3. The FMCB NRZ Tab 4.2.5.4. The QSFPDD400 PAM4 Tab 4.2.5.5. The QSFP NRZ Tab 4.2.5.6. The SFP Tab 4.2.5.7. The OSFP Tab
5. Development Kit Hardware and Configuration x
5.1. Configure the FPGA Device by Active Serial (AS) Modes (Default Mode) 5.2. Configure the FPGA Device by Avalon® -ST (AvST) Modes
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Intel® Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Board Overview and Components A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Memory Interfaces A.7. Communication Interfaces A.8. Daughter Cards
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Power Up the Development Kit
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Revision History
A. Development Kit Components
B. Additional Information

A.1.2. Board Components

Table 6.  Board Connector/Switch Description
Connector/Switch Description
J30 12V AUX1 CONN
J55 12V AUX2 CONN
J3 SDM CONN
J38 FAN0 CONN[CORE FET FAN]
J7 FMCA CONN
J9 FMCB CONN
J57 QSFP0 CONN
J27 QSFP-DD0 CONN
J22 QSFP-DD800 CONN
J58 QSFP1 CONN
J48 QSFP-DD1 CONN
J77 SFP CONN
J6 SI5395-2 IN1N CONN
J4 SI5395-2 IN1P CONN
J34 FAN1 CONN[QSFP LEFT FAN]
J79 TEMP SENSOR I2C CONN
J149 CURRENT SENSOR I2C CONN
J43 FAN2 CONN[FPGA FAN]
J37 MCIO CONN
J5 DIMM CONN
J44 FAN3 CONN[QSFP RIGHT FAN]
J45 OSFP CONN
J67 QSFP-DD3 CONN
J66 QSFP2 CONN
J69 QSFP-DD2 CONN
J25 10MHz IN CONN
J12 SI5395-1 IN1N CONN
J8 SI5395-1 IN1P CONN
J17 10MHz OUT CONN
J140 CLOCK I2C CONN
J41 PMBUS CONN
J21 ToD CONN
J31 SI5518 SPI CONN
J42 CLOCK I2C CONN
J16 1PPS IN CONN
J14 1PPS OUT CONN
J56 CY7C68013A I2C CONN
J11 JTAG CONN
J10 USB2.0 CONN
J154 12V HOTSWAP I2C CONN
S19 JTAG SEL SW
S20 MSTR SW
S21 PMBUS_I2C SW
S9 MODE SEL SW
S22 MUX_DIP_SW
S10,S15 SYSTEM SW
S6,S1 USER SW
S7 BOARD POWER ON/OFF SW
Level Two Title