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1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 7 M-Series FPGA IP
3. Design Example Description for External Memory Interfaces Agilex™ 7 M-Series FPGA IP
4. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP Design Example User Guide
2.1. Creating an EMIF Project
2.2. Generating and Configuring the EMIF IP
2.3. Configuring DQ Pin Swizzling
2.4. Generating the Synthesizable EMIF Design Example
2.5. Generating the EMIF Design Example for Simulation
2.6. Pin Placement for Agilex™ 7 M-Series EMIF IP
2.7. Compiling the Agilex™ 7 M-Series EMIF Design Example
2.8. Using the EMIF Design Example with the Test Engine IP
2.9. Generating the EMIF Design Example with the Performance Monitor
2.1.1.3.1. Generating a Custom Memory Preset File for DDR4
2.1.1.3.2. Guidelines for Selecting the DDR4 DRAM Component Package Type
2.1.1.3.3. Generating a Custom Memory Preset File for DDR5
2.1.1.3.4. Guidelines for Selecting the DDR5 DRAM Component Package Type
2.1.1.3.5. Generating a Custom Memory Preset File for LPDDR5
2.3.1. Example: DQ Pin Swizzling Within DQS group for x32 DDR4 interface
2.3.2. Example: Byte Swizzling for a x32 DDR4 interface, using a memory device of x8 width
2.3.3. Combining Pin and Byte Swizzling
2.3.4. Example: Swizzling for a x32 + ECC interface
2.3.5. Example: Swizzling for a 2Ch x32 + ECC interface
2.3.6. Example: Byte Swizzling for Lockstep Configuration
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1.1. Release Information
IP versions are the same as the Quartus® Prime Design Suite software versions up to v19.1. From Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.
The IP versioning scheme (X.Y.Z) number changes from one software version to another. A change in:
- X indicates a major revision of the IP. If you update your Altera Quartus Prime software, you must regenerate the IP.
- Y indicates the IP includes new features. Regenerate your IP to include these new features.
- Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
Item | Description |
---|---|
IP Version | 6.2.0 |
Quartus® Prime | 24.2 |
Release Date | 2024.07.08 |
Note: This documentation is preliminary and subject to change.