External Memory Interfaces Agilex™ 7 M-Series FPGA IP Design Example User Guide

ID 772632
Date 7/08/2024
Public
Document Table of Contents

1.1. Release Information

IP versions are the same as the Quartus® Prime Design Suite software versions up to v19.1. From Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.

The IP versioning scheme (X.Y.Z) number changes from one software version to another. A change in:

  • X indicates a major revision of the IP. If you update your Altera Quartus Prime software, you must regenerate the IP.
  • Y indicates the IP includes new features. Regenerate your IP to include these new features.
  • Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
Item Description
IP Version 6.2.0
Quartus® Prime 24.2
Release Date 2024.07.08
Note: This documentation is preliminary and subject to change.