External Memory Interfaces Agilex™ 7 M-Series FPGA IP Design Example User Guide

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ID 772632
Date 11/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 7 M-Series FPGA IP 3. Design Example Description for External Memory Interfaces Agilex™ 7 M-Series FPGA IP 4. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP Design Example User Guide
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP x
1.1. Release Information
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 7 M-Series FPGA IP x
2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Parameterizing the External Memory Interface for HPS IP 2.4. Configuring DQ Pin Swizzling 2.5. Generating the Synthesizable EMIF Design Example 2.6. Generating the EMIF Design Example for Simulation 2.7. Pin Placement for Agilex™ 7 M-Series EMIF IP 2.8. Compiling the Agilex™ 7 M-Series EMIF Design Example 2.9. Using the EMIF Design Example with the Test Engine IP 2.10. Generating the EMIF Design Example with the Performance Monitor
2.2. Generating and Configuring the EMIF IP x
2.2.1. Agilex™ 7 M-Series EMIF Parameter Editor Guidelines 2.2.2. Using Custom Memory Timing and I/O Configuration
2.3. Parameterizing the External Memory Interface for HPS IP x
2.3.1. Parameterization Flow 2.3.2. Parametering the EMIF HPS IP 2.3.3. Parameterizing the EMIF IP
2.4. Configuring DQ Pin Swizzling x
2.4.1. Example: DQ Pin Swizzling Within DQS group for x32 DDR4 interface 2.4.2. Example: Byte Swizzling for a x32 DDR4 interface, using a memory device of x8 width 2.4.3. Combining Pin and Byte Swizzling 2.4.4. Example: Swizzling for a x32 + ECC interface 2.4.5. Example: Swizzling for a 2Ch x32 + ECC interface 2.4.6. Example: Byte Swizzling for Lockstep Configuration
3. Design Example Description for External Memory Interfaces Agilex™ 7 M-Series FPGA IP x
3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Design Tab
3.2. Simulation Design Example x
3.2.1. Running Simulation
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 7 M-Series FPGA IP
3. Design Example Description for External Memory Interfaces Agilex™ 7 M-Series FPGA IP
4. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP Design Example User Guide

2.1. Creating an EMIF Project

You must create an Quartus® Prime project before generating the Agilex™ 7 M-Series EMIF IP and design example.
  1. Launch the Quartus® Prime software and select File > New Project Wizard. Click Next.

    Figure 2. File Menu
  2. Specify a directory (<user project directory>), a name for the Quartus® Prime project (<user project name>), and a top-level design entity name (<user top-level instance name>) that you want to create.
  3. Verify that Empty Project is selected.
  4. Under Family, select Agilex™ 7 .
  5. Under Name filter, type the device part number.
  6. Under Available devices, select the appropriate device.

    Figure 3. Family, Device, and Board Settings
  7. Click Finish.
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