External Memory Interfaces Agilex™ 7 M-Series FPGA IP Design Example User Guide

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ID 772632
Date 11/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 7 M-Series FPGA IP 3. Design Example Description for External Memory Interfaces Agilex™ 7 M-Series FPGA IP 4. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP Design Example User Guide
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP x
1.1. Release Information
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 7 M-Series FPGA IP x
2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Parameterizing the External Memory Interface for HPS IP 2.4. Configuring DQ Pin Swizzling 2.5. Generating the Synthesizable EMIF Design Example 2.6. Generating the EMIF Design Example for Simulation 2.7. Pin Placement for Agilex™ 7 M-Series EMIF IP 2.8. Compiling the Agilex™ 7 M-Series EMIF Design Example 2.9. Using the EMIF Design Example with the Test Engine IP 2.10. Generating the EMIF Design Example with the Performance Monitor
2.2. Generating and Configuring the EMIF IP x
2.2.1. Agilex™ 7 M-Series EMIF Parameter Editor Guidelines 2.2.2. Using Custom Memory Timing and I/O Configuration
2.3. Parameterizing the External Memory Interface for HPS IP x
2.3.1. Parameterization Flow 2.3.2. Parametering the EMIF HPS IP 2.3.3. Parameterizing the EMIF IP
2.4. Configuring DQ Pin Swizzling x
2.4.1. Example: DQ Pin Swizzling Within DQS group for x32 DDR4 interface 2.4.2. Example: Byte Swizzling for a x32 DDR4 interface, using a memory device of x8 width Example: Byte Swizzling for a x32 DDR4 interface, using a memory device of x8 width 2.4.3. Combining Pin and Byte Swizzling 2.4.4. Example: Swizzling for a x32 + ECC interface 2.4.5. Example: Swizzling for a 2Ch x32 + ECC interface 2.4.6. Example: Byte Swizzling for Lockstep Configuration
3. Design Example Description for External Memory Interfaces Agilex™ 7 M-Series FPGA IP x
3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Design Tab
3.2. Simulation Design Example x
3.2.1. Running Simulation
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 7 M-Series FPGA IP
3. Design Example Description for External Memory Interfaces Agilex™ 7 M-Series FPGA IP
4. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP Design Example User Guide

2.4.2. Example: Byte Swizzling for a x32 DDR4 interface, using a memory device of x8 width

Example: Byte Swizzling for a x32 DDR4 interface, using a memory device of x8 width

Table 7.  
Lane Number BL0 BL1 BL2 BL3 BL4 BL5 BL6 BL7
Default Placement DQ[0] AC[0] AC[1] AC[2] DQ[1] DQ[2] DQ[3] GPIO
After Byte Swizzling DQ[2] AC[0] AC[1] AC[2] DQ[1] DQ[0] DQ[3] GPIO
BYTE SWIZZLE 2 X X X 1 0 3 X

This example illustrates swizzling DQS group 0 with DQS group 2. The BYTE_SWIZZLE_CH0 denotes the DQS group implemented in the lane after the swizzling. X indicates that the lane is not used as a data lane (meaning that it serves as an address/command lane or is not used by the EMIF interface).

To achieve this swizzling, you must enter BYTE_SWIZZLE_CH0=2,X,X,X,1,0,3,X; in the Pin Swizzle Map field in the PHY section of the High-level Configuration tab in the parameter editor.

Figure 20. Swizzling DQS group 0 with DQS group 2
Level Two Title