External Memory Interfaces Agilex™ 7 M-Series FPGA IP Design Example User Guide

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ID 772632
Date 11/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 7 M-Series FPGA IP 3. Design Example Description for External Memory Interfaces Agilex™ 7 M-Series FPGA IP 4. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP Design Example User Guide
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP x
1.1. Release Information
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 7 M-Series FPGA IP x
2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Parameterizing the External Memory Interface for HPS IP 2.4. Configuring DQ Pin Swizzling 2.5. Generating the Synthesizable EMIF Design Example 2.6. Generating the EMIF Design Example for Simulation 2.7. Pin Placement for Agilex™ 7 M-Series EMIF IP 2.8. Compiling the Agilex™ 7 M-Series EMIF Design Example 2.9. Using the EMIF Design Example with the Test Engine IP 2.10. Generating the EMIF Design Example with the Performance Monitor
2.2. Generating and Configuring the EMIF IP x
2.2.1. Agilex™ 7 M-Series EMIF Parameter Editor Guidelines 2.2.2. Using Custom Memory Timing and I/O Configuration
2.3. Parameterizing the External Memory Interface for HPS IP x
2.3.1. Parameterization Flow 2.3.2. Parametering the EMIF HPS IP 2.3.3. Parameterizing the EMIF IP
2.4. Configuring DQ Pin Swizzling x
2.4.1. Example: DQ Pin Swizzling Within DQS group for x32 DDR4 interface 2.4.2. Example: Byte Swizzling for a x32 DDR4 interface, using a memory device of x8 width 2.4.3. Combining Pin and Byte Swizzling 2.4.4. Example: Swizzling for a x32 + ECC interface 2.4.5. Example: Swizzling for a 2Ch x32 + ECC interface 2.4.6. Example: Byte Swizzling for Lockstep Configuration
3. Design Example Description for External Memory Interfaces Agilex™ 7 M-Series FPGA IP x
3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Design Tab
3.2. Simulation Design Example x
3.2.1. Running Simulation
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 7 M-Series FPGA IP
3. Design Example Description for External Memory Interfaces Agilex™ 7 M-Series FPGA IP
4. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP Design Example User Guide

2.2.1. Agilex™ 7 M-Series EMIF Parameter Editor Guidelines

This topic provides high-level guidance for parameterizing the tabs in the Agilex™ 7 M-Series EMIF IP parameter editor.
Table 1.  EMIF Parameter Editor Guidelines
Section Name Guidelines
Memory Device

Ensure that you correctly enter the following parameters:

  • Number of channels. (If the device is a DIMM, this specifies the full DQ width of the DIMM. If the interface is composed of discrete components, this specifies the DQ width of each discrete component.)
  • Data DQ Width.
  • ECC DQ Width.
  • Die DQ Density.
  • CS Width.
  • Memory Speed Bin.
  • Memory Operating Frequency.
PHY

Select the desired mode to connect the EMIF IP to user logic:

  • Synchronous fabric.
  • Asynchronous fabric.
  • Reference clock
  • NoC mode.
  • A/C placement
  • Pin swizzle map
  • Enable the Debug Toolkit
Advanced: Memory Timing Allows you to modify the timing values.
Advanced: Analog Overrides Allows you to modify the termination, and VREF settings and drive strengths.
Example Design The Example Design tab lets you select which HDL to use for the top-level files, and which file sets you want the design example to generate. You can also enable the performance monitor and modify the length traffic for the traffic generator. You should make these selections before clicking the Generate Example Design... button. The generated design example is a complete EMIF system consisting of the EMIF IP and a driver that generates random traffic to validate the memory interface.
Note:

When using banks 2A and 2B, select Ch0 Bot Sub-Bank/Ch1 Bot Sub-Bank for the AC placement address and command placement parameter. For banks 3A/3B, 3C/3D, or 2C/2D, there are two options available for the AC placement parameter:

  • You must select Ch0 Top Sub-Bank/Ch1 Bot Sub-Bank when placing CH0 address and command pins in the top sub-bank.
  • You must select Ch0 Bot Sub-Bank/Ch1 Top Sub-Bank when placing CH0 address and command pins in the bottom sub-bank.
Figure 6. EMIF Parameter Editor AC Placement Options

When using DIMMs with dual-die components, ensure that you change the CS Width field to 2 and set the appropriate Command-Address Mirroring value.

Figure 7. Command-Address Mirroring

For additional information, refer to the DIMM Support subsection of the DDR5 Data Width Mapping topic in the External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide.

Figure 8. External Memory Interfaces IP Parameter Editor

For detailed information on individual parameters, refer to the appropriate protocol-specific chapter in the External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide.

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