External Memory Interfaces Agilex™ 7 M-Series FPGA IP Design Example User Guide

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ID 772632
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 7 M-Series FPGA IP 3. Design Example Description for External Memory Interfaces Agilex™ 7 M-Series FPGA IP 4. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP Design Example User Guide
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP x
1.1. Release Information
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 7 M-Series FPGA IP x
2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Configuring DQ Pin Swizzling 2.4. Generating the Synthesizable EMIF Design Example 2.5. Generating the EMIF Design Example for Simulation 2.6. Pin Placement for Agilex™ 7 M-Series EMIF IP 2.7. Compiling the Agilex™ 7 M-Series EMIF Design Example 2.8. Using the EMIF Design Example with the Test Engine IP 2.9. Generating the EMIF Design Example with the Performance Monitor
2.1. Creating an EMIF Project x
2.1.1. Generating a Custom Memory Presets File
2.1.1. Generating a Custom Memory Presets File x
2.1.1.1. Memory Device Description IP Parameter Editor Guidelines 2.1.1.2. Saving a Memory Device Presets File 2.1.1.3. Examples for Generating a Custom Memory Presets File
2.1.1.3. Examples for Generating a Custom Memory Presets File x
2.1.1.3.1. Generating a Custom Memory Preset File for DDR4 2.1.1.3.2. Guidelines for Selecting the DDR4 DRAM Component Package Type 2.1.1.3.3. Generating a Custom Memory Preset File for DDR5 2.1.1.3.4. Guidelines for Selecting the DDR5 DRAM Component Package Type 2.1.1.3.5. Generating a Custom Memory Preset File for LPDDR5
2.2. Generating and Configuring the EMIF IP x
2.2.1. Agilex™ 7 M-Series EMIF Parameter Editor Guidelines 2.2.2. Using Custom Memory Device Presets from a File
2.3. Configuring DQ Pin Swizzling x
2.3.1. Example: DQ Pin Swizzling Within DQS group for x32 DDR4 interface 2.3.2. Example: Byte Swizzling for a x32 DDR4 interface, using a memory device of x8 width 2.3.3. Combining Pin and Byte Swizzling 2.3.4. Example: Swizzling for a x32 + ECC interface 2.3.5. Example: Swizzling for a 2Ch x32 + ECC interface 2.3.6. Example: Byte Swizzling for Lockstep Configuration
3. Design Example Description for External Memory Interfaces Agilex™ 7 M-Series FPGA IP x
3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Design Tab
3.2. Simulation Design Example x
3.2.1. Running Simulation
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 7 M-Series FPGA IP
3. Design Example Description for External Memory Interfaces Agilex™ 7 M-Series FPGA IP
4. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP Design Example User Guide

2.3.5. Example: Swizzling for a 2Ch x32 + ECC interface

Table 12.  Byte Swizzling for an RDIMM DDR5 2Ch x 32 + ECC Interface Implemented with Ch0 Top Sub-Bank / Ch1 Bottom Sub-Bank
Scheme BL0 BL1 BL2 BL3 BL4 BL5 BL6 BL7
Ch 0
Default Placement GPIO DQ[ECC] DQ[3] DQ[2] AC0 AC1 DQ[0] DQ[1]
DQS Group Number in Byte Swizzling Notation X ECC 3 2 X X 0 1
After Byte Swizzling X ECC 3 2 X X 1 0
Ch 1
Default Placement DQ[1] DQ[0] AC0 AC1 DQ[2] DQ[3] DQ[ECC] GPIO
DQS Group Number in Byte Swizzling Notation 1 0 X X 2 3 ECC X
After Byte Swizzling 1 0 X X 3 2 ECC X

This example illustrates byte swizzling in Ch0 DQS group 1 (BL7) with DQS group 0 (BL6) and Ch1 DQS group 2 (BL4) with DQS group 3 (BL5). To achieve this swizzling, enter the following BYTE_SWIZZLE_CH0 and BYTE_SWIZZLE_CH1 specification in the USER Extra Parameters:

  • BYTE_SWIZZLE_CH0=X,ECC,3,2,X,X,1,0;
  • BYTE_SWIZZLE_CH1=1,0,X,X,3,2,ECC,X;
Table 13.  Example of DQ Pin Swizzling in Ch0 ECC Lane for a 2Ch x 32 + ECC Interface
Lane Pin Index Default Placement After Swizzling
BL3 47 MEM_DQ[23] MEM_DQ[23]
46 MEM_DQ[22] MEM_DQ[22]
45 MEM_DQ[21] MEM_DQ[20]
44 MEM_DQ[20] MEM_DQ[21]
43    
42 MEM_DM_N[4] MEM_DM_N[4]
41 MEM_DM_C[4] MEM_DM_C[4]
40 MEM_DM_T[4] MEM_DM_T[4]
39 MEM_DQ[19] MEM_DQ[16]
38 MEM_DQ[18] MEM_DQ[19]
37 MEM_DQ[17] MEM_DQ[18]
36 MEM_DQ[16] MEM_DQ[17]
BL1 23 MEM_DQ[39] MEM_DQ[36]
22 MEM_DQ[38] MEM_DQ[37]
21 MEM_DQ[37] MEM_DQ[38]
20 MEM_DQ[36] MEM_DQ[39]
19    
18 MEM_DM_N[4] MEM_DM_N[4]
17 MEM_DM_C[4] MEM_DM_C[4]
16 MEM_DM_T[4] MEM_DM_T[4]
15 MEM_DQ[35] MEM_DQ[34]
14 MEM_DQ[34] MEM_DQ[35]
13 MEM_DQ[33] MEM_DQ[32]
12 MEM_DQ[32] MEM_DQ[33]

To achieve the pin swizzling shown in the above table, enter the following BYTE_SWIZZLE_CH0 specification in User Extra Parameters:

PIN_SWIZZLE_CH0_ECC=1,0,3,2,7,6,5,4;

This is a full ECC byte but because it is implemented with x4 devices it must follow the x4 restrictions of placing the lower 4 bits of the byte in the lower half and the upper four bits of the byte in the upper half.

  • PIN_SWIZZLE_CH0_DQS4=17,18,19,16;
  • PIN_SWIZZLE_CH0_DQS5=21,20,22,23;

For x4 device widths, the values in BYTE_SWIZZLE represent the bundles of 2 x4 DQS groups. The lower DQS group of the bundle is connected to the lower half of the byte lane, and the upper DQS group of the bundle is connected to the upper half of the byte lane.

The placement of each DQS bundle and DQS group in this example, after the byte swizzling, follows the pattern shown below:

  • CH0 Bundle 2 is placed on BL3:
    • CH0 DQS4 connected to lower half of BL3
    • CH0 DQS5 connected to upper half of BL3
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