External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 10/02/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

8.3.6. LPDDR5 PCB Layout Guidelines

This section describes PCB layout guidelines for an LPDDR5 interface.

Intel Agilex® 7 M-Series devices support LPDDR5 interfaces only for memory down configuration. The LPDDR5 interface supports both thin and thick PCB stackups. The maximum supported data rates vary depending on the selected topology.