External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 10/02/2023
Public

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3.1.3.2. DDR4 Pin Placement

Table 9.  DDR4 Pin Placement
Lane Number Pin Index x32+ECC * x 32 x16 + ECC * x16
BL7 95 MEM_DQ[39]*      
94 MEM_DQ[38] *      
93 MEM_DQ[37] *      
92 MEM_DQ[36] *      
91        
90 MEM_DM_N[4]      
89 MEM_DQS_C[4]      
88 MEM_DQS_T[4]      
87 MEM_DQ[35] *      
86 MEM_DQ[34] *      
85 MEM_DQ[33] *      
84 MEM_DQ[32] *      
BL6 83 MEM_DQ[31] MEM_DQ[31]    
82 MEM_DQ[30] MEM_DQ[30]    
81 MEM_DQ[29] MEM_DQ[29]    
80 MEM_DQ[28] MEM_DQ[28]    
79        
78 MEM_DM_N[3] MEM_DM_N[3]    
77 MEM_DQS_C[3] MEM_DQS_C[3]    
76 MEM_DQS_T[3] MEM_DQS_T[3]    
75 MEM_DQ[27] MEM_DQ[27]    
74 MEM_DQ[26] MEM_DQ[26]    
73 MEM_DQ[25] MEM_DQ[25]    
72 MEM_DQ[24] MEM_DQ[24]    
BL5 71 MEM_DQ[23] MEM_DQ[23] MEM_DQ[23] *  
70 MEM_DQ[22] MEM_DQ[22] MEM_DQ[22] *  
69 MEM_DQ[21] MEM_DQ[21] MEM_DQ[21] *  
68 MEM_DQ[20] MEM_DQ[20] MEM_DQ[20] *  
67        
66 MEM_DM_N[2] MEM_DM_N[2] MEM_DM_N[2]  
65 MEM_DQS_C[2] MEM_DQS_C[2] MEM_DQS_C[2]  
64 MEM_DQS_T[2] MEM_DQS_T[2] MEM_DQS_T[2]  
63 MEM_DQ[19] MEM_DQ[19] MEM_DQ[19] *  
62 MEM_DQ[18] MEM_DQ[18] MEM_DQ[18] *  
61 MEM_DQ[17] MEM_DQ[17] MEM_DQ[17] *  
60 MEM_DQ[16] MEM_DQ[16] MEM_DQ[16] *  
BL4 59 MEM_DQ[15] MEM_DQ[15] MEM_DQ[15] MEM_DQ[15]
58 MEM_DQ[14] MEM_DQ[14] MEM_DQ[14] MEM_DQ[14]
57 MEM_DQ[13] MEM_DQ[13] MEM_DQ[13] MEM_DQ[13]
56 MEM_DQ[12] MEM_DQ[12] MEM_DQ[12] MEM_DQ[12]
55        
54 MEM_DM_N[1] MEM_DM_N[1] MEM_DM_N[1] MEM_DM_N[1]
53 MEM_DQS_C[1] MEM_DQS_C[1] MEM_DQS_C[1] MEM_DQS_C[1]
52 MEM_DQS_T[1] MEM_DQS_T[1] MEM_DQS_T[1] MEM_DQS_T[1]
51 MEM_DQ[11] MEM_DQ[11] MEM_DQ[11] MEM_DQ[11]
50 MEM_DQ[10] MEM_DQ[10] MEM_DQ[10] MEM_DQ[10]
49 MEM_DQ[9] MEM_DQ[9] MEM_DQ[9] MEM_DQ[9]
48 MEM_DQ[8] MEM_DQ[8] MEM_DQ[8] MEM_DQ[8]
BL3 47 MEM_BG[0] MEM_BG[0] MEM_BG[0] MEM_BG[0]
46 MEM_BA[1] MEM_BA[1] MEM_BA[1] MEM_BA[1]
45 MEM_BA[0] MEM_BA[0] MEM_BA[0] MEM_BA[0]
44 MEM_ALERT_N[0] MEM_ALERT_N[0] MEM_ALERT_N[0] MEM_ALERT_N[0]
43 MEM_A[16] MEM_A[16] MEM_A[16] MEM_A[16]
42 MEM_A[15] MEM_A[15] MEM_A[15] MEM_A[15]
41 MEM_A[14] MEM_A[14] MEM_A[14] MEM_A[14]
40 MEM_A[13] MEM_A[13] MEM_A[13] MEM_A[13]
39 MEM_A[12] MEM_A[12] MEM_A[12] MEM_A[12]
38 RZQ Site RZQ Site RZQ Site RZQ Site
37 Differential "N-Side" Reference Clock Input Site Differential "N-Side" Reference Clock Input Site Differential "N-Side" Reference Clock Input Site Differential "N-Side" Reference Clock Input Site
36 Differential "P-Side" Reference Clock Input Site Differential "P-Side" Reference Clock Input Site Differential "P-Side" Reference Clock Input Site Differential "P-Side" Reference Clock Input Site
BL2 35 MEM_A[11] MEM_A[11] MEM_A[11] MEM_A[11]
34 MEM_A[10] MEM_A[10] MEM_A[10] MEM_A[10]
33 MEM_A[9] MEM_A[9] MEM_A[9] MEM_A[9]
32 MEM_A[8] MEM_A[8] MEM_A[8] MEM_A[8]
31 MEM_A[7] MEM_A[7] MEM_A[7] MEM_A[7]
30 MEM_A[6] MEM_A[6] MEM_A[6] MEM_A[6]
29 MEM_A[5] MEM_A[5] MEM_A[5] MEM_A[5]
28 MEM_A[4] MEM_A[4] MEM_A[4] MEM_A[4]
27 MEM_A[3] MEM_A[3] MEM_A[3] MEM_A[3]
26 MEM_A[2] MEM_A[2] MEM_A[2] MEM_A[2]
25 MEM_A[1] MEM_A[1] MEM_A[1] MEM_A[1]
24 MEM_A[0] MEM_A[0] MEM_A[0] MEM_A[0]
BL1 23 MEM_PAR[0] MEM_PAR[0] MEM_PAR[0] MEM_PAR[0]
22 MEM_CS_N[1] MEM_CS_N[1] MEM_CS_N[1] MEM_CS_N[1]
21 MEM_CK_C[0] MEM_CK_C[0] MEM_CK_C[0] MEM_CK_C[0]
20 MEM_CK_T[0] MEM_CK_T[0] MEM_CK_T[0] MEM_CK_T[0]
19 MEM_CKE[1] MEM_CKE[1] MEM_CKE[1] MEM_CKE[1]
18 MEM_CKE[0] MEM_CKE[0] MEM_CKE[0] MEM_CKE[0]
17 MEM_ODT[1] MEM_ODT[1] MEM_ODT[1] MEM_ODT[1]
16 MEM_ODT[0] MEM_ODT[0] MEM_ODT[0] MEM_ODT[0]
15 MEM_ACT_N[0] MEM_ACT_N[0] MEM_ACT_N[0] MEM_ACT_N[0]
14 MEN_CS_N[0] MEN_CS_N[0] MEN_CS_N[0] MEN_CS_N[0]
13 MEM_RESET_N[0] MEM_RESET_N[0] MEM_RESET_N[0] MEM_RESET_N[0]
12 MEM_BG[1] MEM_BG[1] MEM_BG[1] MEM_BG[1]
BL0 11 MEM_DQ[7] MEM_DQ[7] MEM_DQ[7] MEM_DQ[7]
10 MEM_DQ[6] MEM_DQ[6] MEM_DQ[6] MEM_DQ[6]
9 MEM_DQ[5] MEM_DQ[5] MEM_DQ[5] MEM_DQ[5]
8 MEM_DQ[4] MEM_DQ[4] MEM_DQ[4] MEM_DQ[4]
7        
6 MEM_DM_N[0] MEM_DM_N[0] MEM_DM_N[0] MEM_DM_N[0]
5 MEM_DQS_C[0] MEM_DQS_C[0] MEM_DQS_C[0] MEM_DQS_C[0]
4 MEM_DQS_T[0] MEM_DQS_T[0] MEM_DQS_T[0] MEM_DQS_T[0]
3 MEM_DQ[3] MEM_DQ[3] MEM_DQ[3] MEM_DQ[3]
2 MEM_DQ[2] MEM_DQ[2] MEM_DQ[2] MEM_DQ[2]
1 MEM_DQ[1] MEM_DQ[1] MEM_DQ[1] MEM_DQ[1]
0 MEM_DQ[0] MEM_DQ[0] MEM_DQ[0] MEM_DQ[0]
Note: The presence of an asterisk (*) in the above table indicates an ECC byte location.