External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 10/02/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.2.4.1. Address and Command Pin Placement for DDR4

Table 79.  Address and Command Pin Placement for DDR4 IP
Address/Command Lane Index Within Byte Lane DDR4
Scheme 1 Scheme 1A Scheme 2 Scheme 3 Scheme 3A
AC3 11 CK_C[1] CK_C[1] Not used by Address/Command pins in this scheme. CK_C[1] CK_C[1]
10 CK_T[1] CK_T[1] CK_T[1] CK_T[1]
9        
8   ALERT_N   ALERT_N
7        
6        
5        
4        
3        
2        
1        
0     C[0] C[0]
AC2 11 BG[0] BG[0] BG[0] BG[0] BG[0]
10 BA[1] BA[1] BA[1] BA[1] BA[1]
9 BA[0] BA[0] BA[0] BA[0] BA[0]
8 ALERT_N A[17] ALERT_N ALERT_N A[17]
7 A[16] A[16] A[16] A[16] A[16]
6 A[15] A[15] A[15] A[15] A[15]
5 A[14] A[14] A[14] A[14] A[14]
4 A[13] A[13] A[13] A[13] A[13]
3 A[12] A[12] A[12] A[12] A[12]
2 RZQ site
1 Differential "N-side" reference clock input site.
0 Differential "P-side" reference clock input site.
AC1 11 A[11] A[11] A[11] A[11] A[11]
10 A[10] A[10] A[10] A[10] A[10]
9 A[9] A[9] A[9] A[9] A[9]
8 A[8] A[8] A[8] A[8] A[8]
7 A[7] A[7] A[7] A[7] A[7]
6 A[6] A[6] A[6] A[6] A[6]
5 A[5] A[5] A[5] A[5] A[5]
4 A[4] A[4] A[4] A[4] A[4]
3 A[3] A[3] A[3] A[3] A[3]
2 A[2] A[2] A[2] A[2] A[2]
1 A[1] A[1] A[1] A[1] A[1]
0 A[0] A[0] A[0] A[0] A[0]
AC0 11 PAR[0] PAR[0] PAR[0] PAR[0] PAR[0]
10 CS_N[1] CS_N[1] CS_N[1] CS_N[1] CS_N[1]
9 CK_C[0] CK_C[0] CK_C[0] CK_C[0] CK_C[0]
8 CK_T[0] CK_T[0] CK_T[0] CK_T[0] CK_T[0]
7 CKE[1] CKE[1] CKE[1] CKE[1] CKE[1]
6 CKE[0] CKE[0] CKE[0] CKE[0] CKE[0]
5 ODT[1] ODT[1] ODT[1] ODT[1] ODT[1]
4 ODT[0] ODT[0] ODT[0] ODT[0] ODT[0]
3 ACT_N[0] ACT_N[0] ACT_N[0] ACT_N[0] ACT_N[0]
2 CS_N[0] CS_N[0] CS_N[0] CS_N[0] CS_N[0]
1 RESET_N[0] RESET_N[0] RESET_N[0] RESET_N[0] RESET_N[0]
0 BG[1] BG[1] BG[1] BG[1] BG[1]

Intel Agilex® 7 M-Series FPGA DDR4 IP supports fixed Address and Command pin placement as shown in the preceding table. The IP supports up to 2 ranks for the following schemes:

  • Scheme 1 supports component, UDIMM, RDIMM, and SODIMM.
  • Scheme 1A supports x4 component and RDIMM with A[17] (that is, with 16Gb, x4 DQ/DQS group base component).
  • Scheme 2 supports component, UDIMM, RDIMM, and SODIMM. Scheme 2 is the only scheme for HPS DDR4 EMIF, available for fabric EMIF as well.
  • Schemes 3 and 3A are similar to schemes 1 and 1A. Schemes 3 and 3A support 3DS for component, UDIMM, RDIMM, and SODIMM. The maximum supported 3DS height is 2.