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1. Answers to Top FAQs
2. Network-on-Chip (NoC) Overview
3. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs
4. NoC Design Flow in Intel® Quartus® Prime Pro Edition
5. NoC Real-time Performance Monitoring
6. Simulating NoC Designs
7. NoC Power Estimation
8. Hard Memory NoC IP Reference
9. Document Revision History of Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide
4.4.1. General NoC IP Connectivity Guidelines
4.4.2. Connectivity Guidelines: NoC Initiators for Fabric AXI4 Managers
4.4.3. Connectivity Guidelines: NoC Targets for Fabric AXI4 Managers
4.4.4. Connectivity Guidelines: NoC Clock Control
4.4.5. Connectivity Guidelines: NoC Initiators for HPS
4.4.6. Connectivity Guidelines: NoC Targets for HPS
6.1. Adding NoC Connectivity and Address Mapping to the Simulation Netlist
6.2. Generating a Simulation Registration Include File (NoC Assignment Editor Connection Flow)
6.3. Generating a Simulation Registration Include File (Platform Designer Connection Flow)
6.4. Contents of Simulation Registration Include File
8.1.2.1. NoC Initiator Intel FPGA IP AXI4/AXI4 Lite Interfaces
8.1.2.2. NoC Initiator AXI4 User Interface Signals
8.1.2.3. NoC Initiator Intel FPGA IP AXI4 Lite User Interface Signals
8.1.2.4. NoC Initiator Intel FPGA IP Clock and Reset Signals
8.1.2.5. NoC Initiator Intel FPGA IP Platform Designer-Only Signals
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4.5.2.4. Step 4: Validate Logical NoC Assignments and Generate Simulation File
After creating all necessary group, connection, and attribute assignments in the NoC Assignment Editor, follow these steps to validate the logical NoC assignments and generate the simulation file for the NoC:
- Click the Validate button on the NoC Assignment Editor. Validation performs design rule checks, such as ensuring that there is exactly one PLL in each NoC group, and that each NoC initiator has at least one connection. Additionally, validation ensures there are no address space overlaps in your base address assignments. Any design rule check violations display in the lower portion of the NoC Assignment Editor.
- After resolving any errors or warnings, click the Save button to write the assignments to the project .qsf. The registration include file for simulation includes information from the NoC logical assignments.
- If your design uses the NoC Assignment Editor connection flow, as NoC Design Flow Options describes, re-run Analysis & Elaboration to update the registration include file after you make any change to these assignments using either the NoC Assignment Editor or directly in the .qsf.
- After completing logical assignments, run Analysis & Synthesis to prepare the design to make physical assignments using the Interface Planner.
For more details on the registration include file and the NoC simulation flow, refer to Simulating NoC Designs.