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1. Answers to Top FAQs
2. Network-on-Chip (NoC) Overview
3. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs
4. NoC Design Flow in Intel® Quartus® Prime Pro Edition
5. NoC Real-time Performance Monitoring
6. Simulating NoC Designs
7. NoC Power Estimation
8. Hard Memory NoC IP Reference
9. Document Revision History of Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide
4.4.1. General NoC IP Connectivity Guidelines
4.4.2. Connectivity Guidelines: NoC Initiators for Fabric AXI4 Managers
4.4.3. Connectivity Guidelines: NoC Targets for Fabric AXI4 Managers
4.4.4. Connectivity Guidelines: NoC Clock Control
4.4.5. Connectivity Guidelines: NoC Initiators for HPS
4.4.6. Connectivity Guidelines: NoC Targets for HPS
6.1. Adding NoC Connectivity and Address Mapping to the Simulation Netlist
6.2. Generating a Simulation Registration Include File (NoC Assignment Editor Connection Flow)
6.3. Generating a Simulation Registration Include File (Platform Designer Connection Flow)
6.4. Contents of Simulation Registration Include File
8.1.2.1. NoC Initiator Intel FPGA IP AXI4/AXI4 Lite Interfaces
8.1.2.2. NoC Initiator AXI4 User Interface Signals
8.1.2.3. NoC Initiator Intel FPGA IP AXI4 Lite User Interface Signals
8.1.2.4. NoC Initiator Intel FPGA IP Clock and Reset Signals
8.1.2.5. NoC Initiator Intel FPGA IP Platform Designer-Only Signals
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8.1.1. NoC Initiator Intel FPGA IP Parameters
The following parameters are available in the NoC Initiator Intel FPGA IP parameter editor:
Parameter | Description |
---|---|
Per-interface clock and reset signals for AXI4 and AXI4 Lite interfaces | If enabled, each top-level AXI4 or AXI4 Lite interface has its own aclk and aresetn signal. Otherwise, there is a single clock and reset that all AXI4 interfaces share, and another clock and reset that all AXI4 Lite interfaces share. |
Number of AXI4 interfaces | Specifies the number of AXI4 interfaces. Each AXI4 interface is associated with its own physical NoC initiator bridge. |
AXI4 Data Mode | The data mode of the AXI4 interface controls the width of the read and write data and user signals. When you select options with a read data width of 512 or 576 bits, vertical fabric NoC networks deliver read response data deep into the fabric. AXI4 data signal widths are always a power of two. When you select 288- or 576-bit widths, the WUSER and RUSER signals carry the extra bits. |
AXI4 interface handshaking | You can choose how the IP implements the standard AXI handshake where data transfer occurs when you assert READY and VALID. The default implementation includes pipelining registers that may improve fMAX. There is also a low-area implementation available without these pipelining registers. |
Clock(s) of wide read and write AXI channels are independent from the NoC initiator hardware clock | When you select both read and write data widths of >= 512 bits, you can also choose to drive the wide interfaces with a clock that is independent from the clock supplied to the 256b NoC initiator hardware. Use this option for best system-level performance. |
Number of AXI4 Lite interfaces | Sets the number of AXI4 Lite interfaces associated with the first physical NoC initiator. Use AXI4 Lite interfaces to access control and status registers of peripherals on the hard memory NoC. You can only configure the NoC Initiator Intel FPGA IP to expose AXI4 Lite interfaces when the configured AXI4 interfaces are less than or equal to 256 bits in width (or when the AXI4 interface is unused). |
NoC QoS Mode | Specifies whether hard memory NoC Quality of Service traffic originating from this NoC Initiator Intel FPGA IP is driven by AXI QoS signals, or is generated by the hard memory NoC initiator hardware (NOC Bridge generated). |
NoC bridge generated Read Priority | If you select the QoS mode of NOC Bridge generated, select the read priority level for the hard memory NoC initiator QoS Generator. When priority level is 0, read traffic originated by this initiator has the lowest priority on the NoC. Priority level 3 traffic has the highest priority in the hard memory NoC. |
NoC bridge generated Write Priority | If you select the QoS mode of NOC Bridge generated, select the write priority level for the hard memory NoC initiator QoS Generator. When priority level is 0, write traffic originated by this initiator has the lowest priority on the NoC. Priority level 3 traffic has the highest priority in the hard memory NoC. |
Figure 37. Parameter Editor for NoC Initiator Intel FPGA IP (256 Bit)
Figure 38. Parameter Editor for NoC Initiator Intel FPGA IP (512 Bit)