Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

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ID 768844
Date 7/05/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Network-on-Chip (NoC) Overview 3. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs 4. NoC Design Flow in Intel® Quartus® Prime Pro Edition 5. NoC Real-time Performance Monitoring 6. Simulating NoC Designs 7. NoC Power Estimation 8. Hard Memory NoC IP Reference 9. Document Revision History of Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide
2. Network-on-Chip (NoC) Overview x
2.1. Introduction to Intel Agilex® 7 M-Series FPGAs 2.2. Terminology for Intel Agilex® 7 M-Series FPGAs 2.3. General NoC Architecture and Applications
2.3. General NoC Architecture and Applications x
2.3.1. General NoC Architecture 2.3.2. Example NoC Applications
2.3.2. Example NoC Applications x
2.3.2.1. Parallel Computing NoC Application 2.3.2.2. SmartNIC NoC Application
3. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs x
3.1. High-Level Architecture 3.2. NoC Segments 3.3. NoC Switch and Link Detail 3.4. Fabric NoC 3.5. NoC Protocol Support 3.6. NoC Design Considerations
3.2. NoC Segments x
3.2.1. UIB Segments 3.2.2. GPIO-B Segments 3.2.3. GPIO-B and HPS Segment 3.2.4. SDM Segment 3.2.5. PLL and SSM Segment
3.5. NoC Protocol Support x
3.5.1. AXI4 Protocol Support 3.5.2. AXI4 Handshaking Support 3.5.3. Quality of Service (QoS) Support 3.5.4. Transaction Ordering Support 3.5.5. AXI4 Lite Protocol Support
3.6. NoC Design Considerations x
3.6.1. Determining the Number of NoC Targets 3.6.2. Determining the Number of NoC Initiators 3.6.3. Fabric NoC Considerations 3.6.4. Latency Considerations 3.6.5. Initiator and Target Bandwidth Considerations 3.6.6. Horizontal Bandwidth Considerations 3.6.7. GPIO-B Bypass Mode and Initiators
4. NoC Design Flow in Intel® Quartus® Prime Pro Edition x
4.1. Hard Memory NoC Design Flow Overview 4.2. Using NoC Example Designs 4.3. NoC Building Blocks 4.4. Connecting NoC IP 4.5. Making NoC Logical Assignments 4.6. (Recommended) Make NoC Physical Assignments Using Interface Planner 4.7. Compiling the NoC Design
4.1. Hard Memory NoC Design Flow Overview x
4.1.1. NoC Design Flow Options
4.3. NoC Building Blocks x
4.3.1. NoC Initiators for Hard Processor Systems 4.3.2. NoC Targets for Hard Processor Systems 4.3.3. NoC Initiators for Fabric AXI4 Managers 4.3.4. NoC Targets for Fabric AXI4 Managers 4.3.5. NoC Clock Control
4.4. Connecting NoC IP x
4.4.1. General NoC IP Connectivity Guidelines 4.4.2. Connectivity Guidelines: NoC Initiators for Fabric AXI4 Managers 4.4.3. Connectivity Guidelines: NoC Targets for Fabric AXI4 Managers 4.4.4. Connectivity Guidelines: NoC Clock Control 4.4.5. Connectivity Guidelines: NoC Initiators for HPS 4.4.6. Connectivity Guidelines: NoC Targets for HPS
4.4.1. General NoC IP Connectivity Guidelines x
4.4.1.1. Connecting NoC IP and Assigning Base Addresses in the Platform Designer Connection Flow 4.4.1.2. Connecting NoC IP and Assigning Base Addresses in the NoC Assignment Editor Connection Flow
4.5. Making NoC Logical Assignments x
4.5.1. Creating NoC Assignments for Compilation 4.5.2. Using the NoC Assignment Editor
4.5.2. Using the NoC Assignment Editor x
4.5.2.1. Step 1: Make Group Assignments in the NoC Assignment Editor 4.5.2.2. Step 2: Make Connection Assignments in the NoC Assignment Editor 4.5.2.3. Step 3: Make Attribute Assignments in the NoC Assignment Editor 4.5.2.4. Step 4: Validate Logical NoC Assignments and Generate Simulation File
4.6. (Recommended) Make NoC Physical Assignments Using Interface Planner x
4.6.1. Using Interface Planner 4.6.2. Recommended Placement Order for NoC Elements in Interface Planner 4.6.3. Hard Memory NoC Locations in Interface Planner 4.6.4. NoC Performance Reports in Interface Planner
4.7. Compiling the NoC Design x
4.7.1. Fitter NoC Reports 4.7.2. Viewing NoC Elements in Chip Planner
6. Simulating NoC Designs x
6.1. Adding NoC Connectivity and Address Mapping to the Simulation Netlist 6.2. Generating a Simulation Registration Include File (NoC Assignment Editor Connection Flow) 6.3. Generating a Simulation Registration Include File (Platform Designer Connection Flow) 6.4. Contents of Simulation Registration Include File
7. NoC Power Estimation x
7.1. Using the Intel FPGA PTC to Estimate NoC Power
8. Hard Memory NoC IP Reference x
8.1. NoC Initiator Intel FPGA IP 8.2. NoC Clock Control Intel FPGA IP
8.1. NoC Initiator Intel FPGA IP x
8.1.1. NoC Initiator Intel FPGA IP Parameters 8.1.2. NoC Initiator Intel FPGA IP Interfaces
8.1.2. NoC Initiator Intel FPGA IP Interfaces x
8.1.2.1. NoC Initiator Intel FPGA IP AXI4/AXI4 Lite Interfaces 8.1.2.2. NoC Initiator AXI4 User Interface Signals 8.1.2.3. NoC Initiator Intel FPGA IP AXI4 Lite User Interface Signals 8.1.2.4. NoC Initiator Intel FPGA IP Clock and Reset Signals 8.1.2.5. NoC Initiator Intel FPGA IP Platform Designer-Only Signals
8.2. NoC Clock Control Intel FPGA IP x
8.2.1. NoC Clock Control Intel FPGA IP Parameters 8.2.2. NoC Clock Control Intel FPGA IP Interfaces 8.2.3. NoC Clock Control Intel FPGA IP Platform Designer-only Signals
1. Answers to Top FAQs
2. Network-on-Chip (NoC) Overview
3. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs
4. NoC Design Flow in Intel® Quartus® Prime Pro Edition
5. NoC Real-time Performance Monitoring
6. Simulating NoC Designs
7. NoC Power Estimation
8. Hard Memory NoC IP Reference
9. Document Revision History of Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

4.3.3. NoC Initiators for Fabric AXI4 Managers

Configure hard memory NoC initiators for fabric AXI4 managers using the NoC Initiator Intel FPGA IP in either IP Catalog or Platform Designer. Access the NoC Initiator Intel FPGA IP in the IP Catalog by expanding the Intel FPGA Interconnect category, and then expanding the NoC subcategory.

The NoC Initiator Intel FPGA IP allows the creation of multiple AXI4 and AXI4 Lite interfaces using the same configuration that interfaces to the same hard memory NoC subsystem. If your design requires NoC initiators with different configurations, or if your design uses both hard memory NoC subsystems along the top edge and bottom edge of the die, this configuration requires separate NoC Initiator Intel FPGA IP. Each AXI4 interface in the NoC Initiator Intel FPGA IP maps to one hard memory NoC initiator bridge.

In the IP parameter editor, you specify the following parameters for the IP instance:

  • Specify a value for the Number of AXI4 interfaces and Number of AXI4 Lite interfaces. Each AXI4 interface is associated with its own physical NoC initiator bridge. AXI4 Lite interfaces, used to access control and status registers of NoC peripherals, are associated with the first physical NoC initiator bridge. If an instance of the NoC initiator IP has the number of AXI4 interfaces set to 0, that instance uses only one NoC initiator bridge that carries the AXI Lite transactions from all the exposed AXI Lite interfaces.
  • Specify whether the AXI4 and AXI4 Lite interfaces have per-interface clock and reset signals, or whether the interfaces share these signals. If you do not configure for per-interface clock and reset signals, the IP exposes a single shared clock sink and reset sink interface for all AXI4 interfaces, and exposes a separate shared clock sink and reset sink for all AXI4 Lite interfaces.
  • Select the data width for read and write interfaces using the AXI4 Data Mode parameter. Selections with read data width of 512 or 576 bits implement the fabric NoC to transport read response data directly into M20K memory blocks. If you select data widths of 288 or 576 bits, the AXI4 WUSER and RUSER signals carry the extra data bits.
  • If using a 512 or 576 bit wide data mode, additionally specify whether the wide interfaces use an independent clock from the 256-bit NoC initiator hardware. Enable this option for best system-level performance when using wide data modes.
  • Use the AXI4 interface handshaking parameter to optimize the interface handshaking for either fMAX or area. AXI4 Handshaking Support describes this option.
  • Use the NoC QoS Mode parameter to specify whether AXI4 priority applies individually on each AXI4 transaction (AXI QoS option), or hard codes a single priority level into each interface (NOC Bridge generated option). For QoS details, refer to Quality of Service (QoS). If using the NoC Bridge generated option, additionally select the hard-coded values for NoC priority for Reads and NoC priority for Writes.

For example, Figure 20. Parameter Editor for NoC Initiator Intel FPGA IP shows the following NoC Initiator Intel FPGA IP configuration:

  • The IP instance has 16 AXI4 interfaces and 0 AXI4 Lite interfaces.
  • The AXI4 read and write channels are configured for 512-bit wide transactions. Since the interface is symmetrical, one AXI interface is exposed, which includes all 5 AXI channels (R, AR, W, AW, B).
  • Configuration with an AXI4 data mode using 512 bit data paths indicates this IP is implemented using the fabric NoC.
  • Clock(s) of wide read and write AXI channels are independent from the NoC initiator hardware clock. As a result, the read channels (R, AR) are implemented on the NOC clock domain, while the write channels (W, B, AW) use a different clock (noc_bridge_fabric_clk). This independence allows faster clocking of the INIU-facing portion of the write path. However, regardless of the value of this option, the user-facing AXI interface is clocked from the user clock (s0_axi4_clock).
  • This IP uses the default AXI standard for interface handshaking (Fmax optimized). The NoC urgency level of each transaction is based on the AXI AxQOS value associated with each read or write command.
Figure 20. Parameter Editor for NoC Initiator Intel FPGA IP


For full details on the NoC Initiator Intel FPGA IP, refer to NoC Initiator Intel FPGA IP

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