Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 7/05/2023
Public

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4.3.5. NoC Clock Control

Configure the clock control for the hard memory NoC using the NoC Clock Control Intel FPGA IP in either IP Catalog or Platform Designer. Access the NoC Clock Control Intel FPGA IP in the IP Catalog by expanding the Intel FPGA Interconnect category, and then expanding the NoC subcategory.

The NoC Clock Control Intel FPGA IP includes the NoC PLL that provides clocking to the hard memory NoC. The NoC Clock Control Intel FPGA also includes the NoC SSM that configures the hard memory NoC. The NoC SSM provides access to the hard memory NoC performance counters over the service network parallel to the main switch network.

The hard memory NoC along the top edge of the die, and the hard memory NoC along the bottom edge of the die, each requires its own clock control instance. If your design does not use the hard memory NoC along one edge of the die, that hard memory NoC does not require a clock control.

There is only one parameter to configure in the NoC Clock Control Intel FPGA IP. Specify the Reference Clock Frequency for the NoC PLL. Available options are 25, 100, or 125 MHz.

For details on the NoC Clock Control Intel FPGA IP, refer to NoC Clock Control Intel FPGA IP.