Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 7/05/2023
Public

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4.4.6. Connectivity Guidelines: NoC Targets for HPS

The External Memory Interfaces for HPS Intel FPGA IP contains the NoC target bridges for HPS. Make any clocking, reset, calibration, or external I/O connections for this IP in accordance with the user guide guidelines for this IP.

  • If you are using the Platform Designer connection flow, as NoC Design Flow Options describes, instantiate your NoC IP in Platform Designer. Connect the AXI4 NoC subordinate interface on the External Memory Interfaces for HPS Intel FPGA IP only to the AXI4 NoC manager interfaces on the Hard Processor System Intel Agilex 7 / Agilex 9 FPGA IP. Do not connect the target bridges in the HPS EMIF IP to any fabric-facing NoC Initiator Intel FPGA IP. After connecting the AXI4 NoC manager and AXI4 NoC subordinate interfaces, click the Address Map tab, to specify the base address for each connection. If an AXI4 NoC manager interface connects to multiple AXI4 NoC subordinate interfaces, ensure each connection has a unique starting address.
  • If you are using the NoC Assignment Editor connection flow, as NoC Design Flow Options describes, instantiate your NoC IP in Platform Designer and leave the AXI4 NoC subordinate interface unconnected. After running Intel® Quartus® Prime Analysis & Elaboration, you can use the NoC Assignment Editor to define connectivity and addressing to prepare your design for RTL simulation. Note that HPS designs only support design entry using Platform Designer. HPS designs do not support direct RTL instantiation.

For details on HPS EMIF IP, refer to refer to the External Memory Interfaces Intel Agilex 7 M-Series FPGA IP User Guide.