Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

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ID 768844
Date 7/05/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Network-on-Chip (NoC) Overview 3. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs 4. NoC Design Flow in Intel® Quartus® Prime Pro Edition 5. NoC Real-time Performance Monitoring 6. Simulating NoC Designs 7. NoC Power Estimation 8. Hard Memory NoC IP Reference 9. Document Revision History of Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide
2. Network-on-Chip (NoC) Overview x
2.1. Introduction to Intel Agilex® 7 M-Series FPGAs 2.2. Terminology for Intel Agilex® 7 M-Series FPGAs 2.3. General NoC Architecture and Applications
2.3. General NoC Architecture and Applications x
2.3.1. General NoC Architecture 2.3.2. Example NoC Applications
2.3.2. Example NoC Applications x
2.3.2.1. Parallel Computing NoC Application 2.3.2.2. SmartNIC NoC Application
3. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs x
3.1. High-Level Architecture 3.2. NoC Segments 3.3. NoC Switch and Link Detail 3.4. Fabric NoC 3.5. NoC Protocol Support 3.6. NoC Design Considerations
3.2. NoC Segments x
3.2.1. UIB Segments 3.2.2. GPIO-B Segments 3.2.3. GPIO-B and HPS Segment 3.2.4. SDM Segment 3.2.5. PLL and SSM Segment
3.5. NoC Protocol Support x
3.5.1. AXI4 Protocol Support 3.5.2. AXI4 Handshaking Support 3.5.3. Quality of Service (QoS) Support 3.5.4. Transaction Ordering Support 3.5.5. AXI4 Lite Protocol Support
3.6. NoC Design Considerations x
3.6.1. Determining the Number of NoC Targets 3.6.2. Determining the Number of NoC Initiators 3.6.3. Fabric NoC Considerations 3.6.4. Latency Considerations 3.6.5. Initiator and Target Bandwidth Considerations 3.6.6. Horizontal Bandwidth Considerations 3.6.7. GPIO-B Bypass Mode and Initiators
4. NoC Design Flow in Intel® Quartus® Prime Pro Edition x
4.1. Hard Memory NoC Design Flow Overview 4.2. Using NoC Example Designs 4.3. NoC Building Blocks 4.4. Connecting NoC IP 4.5. Making NoC Logical Assignments 4.6. (Recommended) Make NoC Physical Assignments Using Interface Planner 4.7. Compiling the NoC Design
4.1. Hard Memory NoC Design Flow Overview x
4.1.1. NoC Design Flow Options
4.3. NoC Building Blocks x
4.3.1. NoC Initiators for Hard Processor Systems 4.3.2. NoC Targets for Hard Processor Systems 4.3.3. NoC Initiators for Fabric AXI4 Managers 4.3.4. NoC Targets for Fabric AXI4 Managers 4.3.5. NoC Clock Control
4.4. Connecting NoC IP x
4.4.1. General NoC IP Connectivity Guidelines 4.4.2. Connectivity Guidelines: NoC Initiators for Fabric AXI4 Managers 4.4.3. Connectivity Guidelines: NoC Targets for Fabric AXI4 Managers 4.4.4. Connectivity Guidelines: NoC Clock Control 4.4.5. Connectivity Guidelines: NoC Initiators for HPS 4.4.6. Connectivity Guidelines: NoC Targets for HPS
4.4.1. General NoC IP Connectivity Guidelines x
4.4.1.1. Connecting NoC IP and Assigning Base Addresses in the Platform Designer Connection Flow 4.4.1.2. Connecting NoC IP and Assigning Base Addresses in the NoC Assignment Editor Connection Flow
4.5. Making NoC Logical Assignments x
4.5.1. Creating NoC Assignments for Compilation 4.5.2. Using the NoC Assignment Editor
4.5.2. Using the NoC Assignment Editor x
4.5.2.1. Step 1: Make Group Assignments in the NoC Assignment Editor 4.5.2.2. Step 2: Make Connection Assignments in the NoC Assignment Editor 4.5.2.3. Step 3: Make Attribute Assignments in the NoC Assignment Editor 4.5.2.4. Step 4: Validate Logical NoC Assignments and Generate Simulation File
4.6. (Recommended) Make NoC Physical Assignments Using Interface Planner x
4.6.1. Using Interface Planner 4.6.2. Recommended Placement Order for NoC Elements in Interface Planner 4.6.3. Hard Memory NoC Locations in Interface Planner 4.6.4. NoC Performance Reports in Interface Planner
4.7. Compiling the NoC Design x
4.7.1. Fitter NoC Reports 4.7.2. Viewing NoC Elements in Chip Planner
6. Simulating NoC Designs x
6.1. Adding NoC Connectivity and Address Mapping to the Simulation Netlist 6.2. Generating a Simulation Registration Include File (NoC Assignment Editor Connection Flow) 6.3. Generating a Simulation Registration Include File (Platform Designer Connection Flow) 6.4. Contents of Simulation Registration Include File
7. NoC Power Estimation x
7.1. Using the Intel FPGA PTC to Estimate NoC Power
8. Hard Memory NoC IP Reference x
8.1. NoC Initiator Intel FPGA IP 8.2. NoC Clock Control Intel FPGA IP
8.1. NoC Initiator Intel FPGA IP x
8.1.1. NoC Initiator Intel FPGA IP Parameters 8.1.2. NoC Initiator Intel FPGA IP Interfaces
8.1.2. NoC Initiator Intel FPGA IP Interfaces x
8.1.2.1. NoC Initiator Intel FPGA IP AXI4/AXI4 Lite Interfaces 8.1.2.2. NoC Initiator AXI4 User Interface Signals 8.1.2.3. NoC Initiator Intel FPGA IP AXI4 Lite User Interface Signals 8.1.2.4. NoC Initiator Intel FPGA IP Clock and Reset Signals 8.1.2.5. NoC Initiator Intel FPGA IP Platform Designer-Only Signals
8.2. NoC Clock Control Intel FPGA IP x
8.2.1. NoC Clock Control Intel FPGA IP Parameters 8.2.2. NoC Clock Control Intel FPGA IP Interfaces 8.2.3. NoC Clock Control Intel FPGA IP Platform Designer-only Signals
1. Answers to Top FAQs
2. Network-on-Chip (NoC) Overview
3. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs
4. NoC Design Flow in Intel® Quartus® Prime Pro Edition
5. NoC Real-time Performance Monitoring
6. Simulating NoC Designs
7. NoC Power Estimation
8. Hard Memory NoC IP Reference
9. Document Revision History of Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

4.6.2. Recommended Placement Order for NoC Elements in Interface Planner

For best results, place NoC-related elements in the following order, starting with the IP containing the NoC targets.

If your design uses HPS, perform the following step:

  1. Click the Autoplace Fixed button to place any elements that have only one legal location. Repeat clicking the Autoplace Fixed button to place directly connected elements until Interface Planner displays the message 'No elements found with only 1 legal location’.

If your design uses HPS and any external memory interfaces associated with the HPS remain unplaced after the previous step, perform the following steps:

  1. For each HPS external memory, expand the IP in the Design Element pane and locate the RZQ pin, the element whose name ends in …oct_rzqin~CLUSTER.
  2. Right-click on this element and click Generate Legal Locations for Selected Elements. The Interface Planner may display multiple legal locations, depending on prior placements.
  3. Select the RZQ pin for the I/O bank that you want to implement your external memory interface. Refer to the pinout tables for your device to identify the RZQ pin associated with the target bank. Note that you must place external memory interfaces for HPS in the I/O bank or banks adjacent to the HPS. Right-click on the desired pin location from the list of legal locations and click Place at Selected.
  4. Click the Autoplace Fixed button to place directly connected elements. Repeat clicking the Autoplace Fixed button until Interface Planner displays the message ‘No elements found with only 1 legal location’. The placement of this IP block is complete and you can proceed to the next IP.

For each HBM2e IP in your design, perform the following steps:

  1. Expand the IP in the Design Element pane and locate the HBM controller, the element whose name ends in “…|xhmbc."
  2. Right-click on this element and click Generate Legal Locations for Selected Elements. The Interface Planner may display one or two legal locations, depending on prior placements.
  3. Select the HBM2e location along the top edge or bottom edge of the die based on your design requirements. Right-click on the desired location from the list of legal locations and click Place at Selected.
  4. Click the Autoplace Fixed button to place directly connected elements. Repeat pressing the Autoplace Fixed button until Interface Planner displays the message ‘No elements found with only 1 legal location’. At this point, the placement of the IP block is complete and you can proceed to the next IP.

For each external memory interface in your design, perform the following steps:

  1. Expand the IP in the Design Element pane and locate the RZQ pin, the element whose name ends in “…oct_rzqin~CLUSTER."
  2. Right-click on this element and click Generate Legal Locations for Selected Elements. The Interface Planner may display multiple legal locations, depending on prior placements.
  3. Select the RZQ pin for the I/O bank that you want to implement your external memory interface. Refer to the pinout tables for your device to identify the RZQ pin associated with the target bank. Right-click on the desired pin location from the list of legal locations and select Place at Selected.
  4. Click the Autoplace Fixed button to place directly connected elements. Repeat pressing the Autoplace Fixed button until Interface Planner displays the message ‘No elements found with only 1 legal location’. At this point, the placement of this IP block is complete and you can proceed to the next IP.

After placing all the IP containing the NoC targets, Interface Planner also places the NoC Clock Control IP containing the NoC PLL and the NoC SSM. These placements are based on the group assignments that you make in the NoC Assignment Editor.

Proceed with placing the NoC initiators by switching to the NoC View. This view shows the target interface bridges that you have placed. As you place each initiator, the tool highlights the targets connected to the initiator. When placing each initiator, consider which targets that initiator accesses. Place the initiator close to the targets that require low-latency or high-bandwidth accesses. Since HBM2e channels are functionally interchangeable, you can also shorten communication paths across the NoC by choosing HBM2e channels that are close to your ideal initiator location.

Note: For important considerations when choosing initiator interface bridge placement, refer to the tables in Horizontal Bandwidth Considerations, along with tables in Hard Memory NoC Locations in Interface Planner to translate location choices into physical placements.

External Memory Interfaces and other GPIO functions that bypass the NOC can conflict with initiator interface bridges placement, as GPIO-B Bypass Mode and Initiators describes. Depending on design requirements, you can place these I/O functions that bypass the NoC before or after placing the NoC initiator interfaces. Placing I/O functions first gives greater flexibility to their placement, while restricting which initiator locations you can use. Placing NoC initiator interface bridges first allows optimal initiator placement, while restricting which I/O locations are available.

Other interfaces, such as transceivers, have no direct interaction with the hard memory NoC. Therefore, you can place such interfaces before or after the NoC.

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