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1. Answers to Top FAQs
2. Network-on-Chip (NoC) Overview
3. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs
4. NoC Design Flow in Intel® Quartus® Prime Pro Edition
5. NoC Real-time Performance Monitoring
6. Simulating NoC Designs
7. NoC Power Estimation
8. Hard Memory NoC IP Reference
9. Document Revision History of Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide
4.4.1. General NoC IP Connectivity Guidelines
4.4.2. Connectivity Guidelines: NoC Initiators for Fabric AXI4 Managers
4.4.3. Connectivity Guidelines: NoC Targets for Fabric AXI4 Managers
4.4.4. Connectivity Guidelines: NoC Clock Control
4.4.5. Connectivity Guidelines: NoC Initiators for HPS
4.4.6. Connectivity Guidelines: NoC Targets for HPS
6.1. Adding NoC Connectivity and Address Mapping to the Simulation Netlist
6.2. Generating a Simulation Registration Include File (NoC Assignment Editor Connection Flow)
6.3. Generating a Simulation Registration Include File (Platform Designer Connection Flow)
6.4. Contents of Simulation Registration Include File
8.1.2.1. NoC Initiator Intel FPGA IP AXI4/AXI4 Lite Interfaces
8.1.2.2. NoC Initiator AXI4 User Interface Signals
8.1.2.3. NoC Initiator Intel FPGA IP AXI4 Lite User Interface Signals
8.1.2.4. NoC Initiator Intel FPGA IP Clock and Reset Signals
8.1.2.5. NoC Initiator Intel FPGA IP Platform Designer-Only Signals
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8.1. NoC Initiator Intel FPGA IP
You use the NoC Initiator Intel FPGA IP to configure AXI4 or AXI4 Lite interfaces between AXI4 managers in your logic and the hard memory NoC. During compilation, the Fitter maps these interfaces to NoC initiator bridges in the hard memory NoC.
Access the NoC Initiator Intel FPGA IP in the IP Catalog by expanding the Intel FPGA Interconnect category, and then expanding the NoC subcategory.