F-Tile JESD204B Intel® FPGA IP User Guide

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ID 723907
Date 4/23/2024
Public
Document Table of Contents
Document Table of Contents x
1. F-Tile JESD204B IP Quick Reference 2. About the F-Tile JESD204B Intel® FPGA IP 3. Getting Started 4. F-Tile JESD204B IP Functional Description 5. F-Tile JESD204B IP Deterministic Latency Implementation Guidelines 6. F-Tile JESD204B IP Debug Guidelines 7. F-Tile JESD204B Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile JESD204B Intel® FPGA IP User Guide
2. About the F-Tile JESD204B Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. Datapath Modes 2.4. IP Variation 2.5. F-Tile JESD204B IP Configuration 2.6. Channel Bonding 2.7. Performance and Resource Utilization
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Intel® FPGA IP Evaluation Mode 3.4. Upgrading IP Cores 3.5. IP Catalog and Parameter Editor 3.6. Design Walkthrough 3.7. F-Tile JESD204B IP Design Considerations 3.8. F-Tile JESD204B Intel® FPGA IP Parameters 3.9. F-Tile JESD204B IP Component Files
3.6. Design Walkthrough x
3.6.1. Creating a New Quartus® Prime Project 3.6.2. Parameterizing and Generating the IP 3.6.3. Compiling the F-Tile JESD204B IP Core Design 3.6.4. Programming an FPGA Device
3.7. F-Tile JESD204B IP Design Considerations x
3.7.1. Integrating the F-Tile JESD204B IP in Platform Designer 3.7.2. Pin Assignments 3.7.3. Adding External System PLL
4. F-Tile JESD204B IP Functional Description x
4.1. Transmitter 4.2. Receiver 4.3. Operation 4.4. Clocking Scheme 4.5. Reset Scheme 4.6. Signals 4.7. Registers
4.1. Transmitter x
4.1.1. TX Data Link Layer 4.1.2. TX PHY Layer
4.1.1. TX Data Link Layer x
4.1.1.1. TX CGS 4.1.1.2. TX ILAS 4.1.1.3. User Data Phase
4.2. Receiver x
4.2.1. RX Data Link Layer 4.2.2. RX PHY Layer
4.2.1. RX Data Link Layer x
4.2.1.1. RX CGS 4.2.1.2. Frame Synchronization 4.2.1.3. Frame Alignment 4.2.1.4. Lane Alignment 4.2.1.5. ILAS Data 4.2.1.6. Initial Lane Synchronization
4.3. Operation x
4.3.1. Operating Modes 4.3.2. Scrambler/Descrambler 4.3.3. SYNC_N Signal 4.3.4. Link Reinitialization 4.3.5. Link Startup Sequence 4.3.6. Error Reporting Through SYNC_N Signal
4.3.1. Operating Modes x
4.3.1.1. Subclass 0 Operating Mode 4.3.1.2. Subclass 1 Operating Mode 4.3.1.3. Subclass 2 Operating Mode
4.4. Clocking Scheme x
4.4.1. Device Clock 4.4.2. Link Clock 4.4.3. Local MultiFrame Clock 4.4.4. Clock Correlation 4.4.5. System PLL Clock
4.5. Reset Scheme x
4.5.1. Reset Sequence 4.5.2. ADC–FPGA Subsystem Reset Sequence 4.5.3. FPGA–DAC Subsystem Reset Sequence
4.6. Signals x
4.6.1. Transmitter Signals 4.6.2. Receiver Signals
4.7. Registers x
4.7.1. Register Access Type Convention 4.7.2. Register Map and Definition 4.7.3. Transmitter Registers 4.7.4. Receiver Registers
5. F-Tile JESD204B IP Deterministic Latency Implementation Guidelines x
5.1. Constraining Incoming SYSREF Signal 5.2. Programmable RBD Offset 5.3. Programmable LMFC Offset 5.4. Maintaining Deterministic Latency during Link Reinitialization
6. F-Tile JESD204B IP Debug Guidelines x
6.1. Clocking Scheme 6.2. F-Tile JESD204B Parameters 6.3. SPI Programming 6.4. Converter and FPGA Operating Conditions 6.5. Signal Polarity and FPGA Pin Assignment
1. F-Tile JESD204B IP Quick Reference
2. About the F-Tile JESD204B Intel® FPGA IP
3. Getting Started
4. F-Tile JESD204B IP Functional Description
5. F-Tile JESD204B IP Deterministic Latency Implementation Guidelines
6. F-Tile JESD204B IP Debug Guidelines
7. F-Tile JESD204B Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile JESD204B Intel® FPGA IP User Guide

4.1.1.2. TX ILAS

When lane alignment sequence is enabled through the csr_lane_sync_en register, the ILAS sequence is transmitted after the CGS phase. The ILAS phase takes up four multiframes. For Subclass 0 mode, you can program the CSR (csr_ilas_multiframe) to extend the ILAS phase to a maximum of 256 multiframes before transitioning to the encoded user data phase. The ILAS data is not scrambled regardless of whether scrambling is enabled or disabled.

The multiframe has the following structure:

  • Each multiframe starts with a /R/ character (K28.0) and ends with a /A/ character (K28.3)
  • The second multiframe transmits the ILAS configuration data. The multiframe starts with /R/ character (K28.0), followed by /Q/ character (K28.4), and then followed by the link configuration data, which consists of 14 octets as illustrated in the table below. It is then padded with dummy data and ends with /A/ character (K28.3), marking the end of multiframe.
  • Dummy octets are an 8-bit counter and is always reset when it is not in ILAS phase.
  • For a configuration of more than four multiframes, the multiframe follows the same rule above and is padded with dummy data in between /R/ character and /A/ character.
Table 12.   Link Configuration Data Transmitted in ILAS Phase
Configuration Octet Bits Description
MSB 6 5 4 3 2 1 LSB
0 DID[7:0] DID = Device ID
1 ADJCNT[3:0] BID[3:0] ADJCNT = Number of adjustment resolution steps 3

BID = Bank ID

2 0 ADJDIR PHADJ LID[4:0]

ADJDIR = Direction to adjust DAC LMFC 3

PHADJ = Phase adjustment request 3

LID = Lane ID

3 SCR 0 0 L[4:0]

SCR = Scrambling enabled/disabled

L = Number of lanes per device (link)

4 F[7:0] F = Number of octets per frame per lane
5 0 0 0 K[4:0] K = Number of frames per multiframe
6 M[7:0] M = Number of converters per device
7 CS[1:0] 0 N[4:0]

CS = Number of control bits per sample

N = Converter resolution

8 SUBCLASSV[2:0] N_PRIME[4:0]

SUBCLASSV = Subclass version

N_PRIME = Total bits per sample

9 JESDV[2:0] S[4:0]

JESDV = JESD204 version

S = Number of samples per converter per frame

10 HD 0 0 CF[4:0]

HD = High Density data format

CF = Number of control words per frame clock per link

11 RES1[7:0] RES1 = Reserved. Set to 8'h00
12 RES2[7:0] RES2 = Reserved. Set to 8'h00
13 FCHK[7:0]

FCHK is the modulus 256 of the sum of the 13 configuration octets above.

The F-Tile JESD204B TX IP core also supports debug feature to continuously stay in ILAS phase without exiting. You can enable this feature by setting the bit in csr_ilas_loop register. There are two modes of entry:

  • RX asserts SYNC_N and deasserts it after CGS phase. This activity triggers the ILAS phase and the CSR stays in ILAS phase indefinitely until this setting changes.
  • Link reinitialization through CSR is initiated. The F-Tile JESD204B IP core transmits /K/ character and causes the RX converter to enter CGS phase. After RX deasserts SYNC_N, the CSR enters ILAS phase and stays in that phase indefinitely until this setting changes.

In ILAS loop, the multiframe transmission is the same where /R/ character (K28.0) marks the start of multiframe and /A/ character (K28.3) marks the end of multiframe, with dummy data in between. The dummy data is an increment of Dx.y.

3 Applies to Subclass 2 only.
Level Two Title