1

Input

TX PLL reference clock for transceiver/tile.

1

Input

TX link clock signal. This clock is equal to the TX data rate divided by 40.

For Subclass 1, you cannot use the output of txphy_clk signal as txlink_clk signal . To sample SYSREF correctly, the core PLL must provide the txlink_clk signal and must be configured as normal operating mode.

1

Input

From User. Async Assertion and Deassertion.

Assertion triggers reset sequence to MAC and PHY(Tile). Reset sequence completion indicated by assertion tx_rst_ack_n.

Deassertion triggers out-of-reset sequence. Out of reset completion indicates by deassertion of tx_rst_ack_n.

User is required to assert this reset if tx_avs_rst_n is asserted.

1

Output

1

Output

To indicate the reset status of the SIP link layer. Async Assertion and Deassertion. (IP use avs_clk or reconfig_xcvr_clk internally). User may optionally observe jesd204_tx_out_of_reset = 1 to indicate SIP out of reset to pulse SYSREF for subclass 1. User must synchronize this signal before use.

0: SIP in reset

1: SIP out of reset

L

Output

TX parallel clock output for the TX transceiver. This clock has the same frequency as txlink_clk signal.

This clock is output as an optional port for user if the txlink_clk and txframe_clk signals are operating at the same frequency in Subclass 0 operating mode.

L

Output

Differential high-speed serial output data. The clock is embedded in the serial data stream.

L

Output

Differential high-speed serial output data. The clock is embedded in the serial data stream. You don't need to connect this signal at the top-level pinout for proper compilation.

1

Input

Signal is synchronous with reconfig_xcvr_clk.

Only available when Transceiver Dynamic Reconfiguration option is enabled.

1

Input

Signal is synchronous with reconfig_xcvr_clk.

Only available when Transceiver Dynamic Reconfiguration option is enabled.

log2(L)+17:0

Input

Signal is synchronous with reconfig_xcvr_clk.

Each XCVR lanes address=18bits. Upper Ceiling(log2(L)) bits are lane select.

Only available when Transceiver Dynamic Reconfiguration option is enabled.

Input

Signal is synchronous with reconfig_xcvr_clk.

Only available when Transceiver Dynamic Reconfiguration option is enabled.

Output

Signal is synchronous with reconfig_xcvr_clk.

Only available when Transceiver Dynamic Reconfiguration option is enabled.

1

Output

Signal is synchronous with reconfig_xcvr_clk.

Only available when Transceiver Dynamic Reconfiguration option is enabled.

Input

Byte Enable. If byteenable[3:0] is 4’b1111, uses 32-bit Dword Access; otherwise uses byte access.

Only available when Transceiver Dynamic Reconfiguration option is enabled.

L*32

Input

Signal is synchronous with txlink_clk.

Indicates a 32-bit user data at txlink_clk clock rate, where four octets are packed into a 32-bit data width per lane. The data format is big endian.

The first octet is located at bit[31:24], followed by bit[23:16], bit[15:8], and the last octet is bit[7:0]. Lane 0 data is always located in the lower 32-bit data. If more than one lane is instantiated, lane 1 is located at bit[63:32], with the first octet position at bit[63:56].

1

Input

Signal is synchronous with txlink_clk.

Indicates whether the data from the transport layer is valid or invalid. The Avalon® streaming sink interface in the TX core cannot be backpressured and assumes that data is always valid on every cycle when the jesd204_tx_link_ready signal is asserted.

• 0—data is invalid
• 1—data is valid

1

Output

Signal is synchronous with txlink_clk.

Indicates that the Avalon® streaming sink interface in the TX core is ready to accept data. The Avalon® streaming sink interface asserts this signal on the JESD204B link state of USER_DATA phase. USER_DATA phase is the period during which the actual user data is transmitted through the transport layer. The ready latency is 0.

1

Output

Indicates that the Avalon® streaming sink interface in the transport layer is ready to accept data. The Avalon® streaming sink interface asserts this signal on the JESD204B link state of ILAS 4^th multiframe and also the USER_DATA phase. The ready latency is 0.

1

Input

The Avalon® memory-mapped interface clock signal. This clock is asynchronous to all the functional clocks in the F-Tile JESD204B IP core. The JESD204B IP core can handle any cross clock ratio and therefore the clock frequency can range from 75 MHz to 125 MHz.

1

Input

This reset is associated with the jesd204_tx_avs_clk signal. This reset is an active low signal. You can assert this reset signal asynchronously but must deassert it synchronously to the jesd204_tx_avs_clk signal. After you deassert this signal, the CPU can configure the CSRs.

1

Input

Signal is synchronous with tx_avs_clk.

When this signal is present, the slave port ignores all Avalon® memory-mapped signals unless this signal is asserted. This signal must be used in combination with read or write. If the Avalon® memory-mapped bus does not support chip select, you are recommended to tie this port to 1.

8

Input

Signal is synchronous with tx_avs_clk.

For Avalon® memory-mapped slave, the interconnect translates the byte address into a word address in the address space so that each slave access is for a word of data. For example, address = 0 selects the first word of the slave and address = 1 selects the second word of the slave.

32

Input

Signal is synchronous with tx_avs_clk.

32-bit data for write transfers. The width of this signal and the jesd204_tx_avs_readdata[31:0] signal must be the same if both signals are present

1

Input

Signal is synchronous with tx_avs_clk.

This signal is asserted to indicate a read transfer. This is an active high signal and requires the jesd204_tx_avs_readdata[31:0] signal to be in use.

1

Input

Signal is synchronous with tx_avs_clk.

This signal is asserted to indicate a write transfer. This is an active high signal and requires the jesd204_tx_avs_writedata[31:0] signal to be in use.

32

Output

Signal is synchronous with tx_avs_clk.

32-bit data driven from the Avalon® memory-mapped slave to master in response to a read transfer.

1

Output

Signal is synchronous with tx_avs_clk.

This signal is asserted by the Avalon® memory-mapped slave to indicate that it is unable to respond to a read or write request. The F-Tile JESD204B IP core ties this signal to 0 to return the data in the access cycle.

1

Input

For Subclass 0 and Subclass 2 mode, tie-off this signal to 0.

1

Input

Indicates SYNC_N from the converter device or receiver. This is an active low signal and is asserted 0 to indicate a synchronization request or error reporting from the converter device.

To indicate a synchronization request, the converter device must assert this signal for at least five frames and nine octets.

To indicate an error reporting, the converter device must ensure that the pulse is at least one cycle of the txlink_clk signal or two cycles of the txframe_clk signal (whichever period is longer).

1

Output

Indicates a clean synchronization request. This is an active low signal and is asserted 0 to indicate a synchronization request only. The sync_n signal error reporting is being masked out of this signal. This signal is also asserted during software-initiated synchronization.

1

Input

Indicates a multidevice synchronization request. Synchronized signal combination should be done externally and then input to the F-Tile JESD204B IP core through this signal.

• For subclass 0—combine the dev_sync_n signal from all multipoint links before connecting to the mdev_sync_n signal.
• For subclass 1—connect the dev_sync_n signal to the mdev_sync_n signal for each link respectively.

In a single link instance where multidevice synchronization is not needed, tie the dev_sync_n signal to this signal.

Indicates a start of multiframe.

• [3]—start of multiframe for jesd204_tx_link_data[31:24]
• [2]—start of multiframe for jesd204_tx_link_data[23:16]
• [1]—start of multiframe for jesd204_tx_link_data[15:8]
• [0]—start of multiframe for jesd204_tx_link_data[7:0]

1

Input

Optional signal to indicate an empty data stream due to invalid data. This signal is asserted high to indicate an error during data transfer from the transport layer to the TX core.

5

Output

Indicates the number of active lanes for the link. The transport layer can use this signal as a run-time parameter.

8

Output

Indicates the number of octets per frame. The transport layer can use this signal as a run-time parameter.

5

Output

Indicates the number of frames per multiframe. The transport layer can use this signal as a run-time parameter.

8

Output

Indicates the number of converters for the link. The transport layer can use this signal as a run-time parameter.

2

Output

Indicates the number of control bits per sample. The transport layer can use this signal as a run-time parameter.

5

Output

Indicates the converter resolution. The transport layer can use this signal as a run-time parameter.

5

Output

Indicates the total number of bits per sample. The transport layer can use this signal as a run-time parameter.

5

Output

Indicates the number of samples per converter per frame cycle. The transport layer can use this signal as a run-time parameter.

1

Output

Indicates the high density data format. The transport layer can use this signal as a run-time parameter.

5

Output

Indicates the number of control words per frame clock period per link. The transport layer can use this signal as a run-time parameter.

L

Output

Indicates which lane is powered down. You need to set this signal if you have configured the link and want to reduce the number of active lanes.

1

Output

Interrupt pin for the F-Tile JESD204B IP core. Interrupt is asserted when any error or synchronization request is detected. Configure the tx_err_enable register to set the type of error that can trigger an interrupt.

L*32

Output

Signal is synchronous with txlink_clk.

Optional signal for parallel data from the DLL in TX to RX loopback testing. ⁹

L*4

Output

Optional signal to indicate the K character value for each byte in TX to RX loopback testing. ⁹

4

Output

Indicates the test mode for the F-Tile JESD204B IP core and the test pattern for the test pattern generator in the design example.

Refer to the tx_test register in the register map.

A 32-bit fixed data pattern for testing purposes, such as short transport layer test pattern. You can configure the fixed data pattern through the TX register user_test_pattern_a (offset 0xD4)

A 32-bit fixed data pattern for testing purposes, such as short transport layer test pattern. You can configure the fixed data pattern through the TX register user_test_pattern_b (offset 0xD8)

A 32-bit fixed data pattern for testing purposes, such as short transport layer test pattern. You can configure the fixed data pattern through the TX register user_test_pattern_c (offset 0xDC)

A 32-bit fixed data pattern for testing purposes, such as short transport layer test pattern. You can configure the fixed data pattern through the TX register user_test_pattern_d (offset 0xE0)