Visible to Intel only — GUID: vsa1646731637743
Ixiasoft
Visible to Intel only — GUID: vsa1646731637743
Ixiasoft
4.7. Registers
The Avalon® Memory-Mapped Interface Responder interface for the JESD204B supports 0 cycle write transaction and 1 cycle read transaction. There is no support for wait-state feature (the avs_waitrequest signal is tied to 0). It does not support byte enable so all transactions are based on 32-bit width field. The interface does not support burst transaction and variable latency.
Each write transfer has a writeWaitTime of 0 cycle while a read transfer has a readWaitTime of 1 cycle and readLatency of 1 cycle.
JESD204B TX registers residing in 1 reset domain and JESD204B RX registers residing in another reset domain. JESD204B TX/RX only decodes 8-bit addressing (byte addressing) with address range up to 0xFFh (256 Byte).