F-Tile JESD204B Intel® FPGA IP User Guide

ID 723907
Date 4/23/2024
Public
Document Table of Contents

3.7.1. Integrating the F-Tile JESD204B IP in Platform Designer

You can integrate the F-Tile JESD204B IP with other Platform Designer components within Platform Designer.

You can connect standard interfaces like clock, reset, Avalon® memory-mapped, Avalon® streaming, and system PLL clock within Platform Designer. However, for conduit interfaces, you are advised to export all those interfaces and handle them outside of Platform Designer. 2 This is because conduit interfaces are not part of the standard interfaces. Thus, there is no guarantee on compatibility between different conduit interfaces.

Note: The Transport Layer provided in this F-Tile JESD204B IP design example is not supported in Platform Designer. Therefore, you must export all interfaces that connect to the Transport Layer (for example, jesd204_tx_link interface) and connect them to a transport layer outside of Platform Designer.
2 You can also connect conduit interfaces within Platform Designer but you must create adapter components to handle all the incompatibility issues like incompatible signal type and width.