F-Tile JESD204B Intel® FPGA IP User Guide

ID 723907
Date 4/23/2024
Public
Document Table of Contents

4.4.1. Device Clock

In a converter device, the sampling clock is typically the device clock.

For the F-Tile JESD204B IP in an FPGA logic device, you need two reference clocks as shown in the JESD204B Subsystem with Separate Transceiver Reference Clock and Core Clock figure. In the dual reference clock design, the device clock is used as the core PLL reference clock and the other reference clock is used as the transceiver PLL reference clock and system PLL reference clock. The available frequency depends on the PLL type, bonding option, number of lanes, and device family. During IP core generation, the Quartus® Prime software recommends the available reference frequency for the transceiver PLL and core PLL based on user selection.

Note: Due to the clock network architecture in the FPGA, Intel recommends that you use the device clock to generate the link clock and use the link clock as the timing reference. You need to use the IOPLL Intel® FPGA IP core to generate the link clock and frame clock. The link clock is used in the F-Tile JESD204B IP (MAC) and the transport layer. You are recommended to supply the reference clock source through a dedicated reference clock pin.

Based on the JESD204B specification for Subclass 1, the device clock is the timing reference and is source synchronous with SYSREF. To achieve deterministic latency, match the board trace length of the SYSREF signal with the device clock. Maintain a constant phase relationship between the device clock and SYSREF signal pairs going to the FPGA and converter devices. Ideally, the SYSREF pulses from the clock generator should arrive at the FPGA and converter devices at the same time. To avoid half link clock latency variation, you must supply the device clock at the same frequency as the link clock.

The JESD204B protocol does not support rate matching. Therefore, you must ensure that the TX or RX device clock (pll_ref_clk) and the PLL reference clock that generates link clock (txlink_clk or rxlink_clk) and frame clock (txframe_clk or rxframe_clk) have 0 ppm variation. Both PLL reference clocks should come from the same clock chip.

Figure 17. JESD204B Subsystem with Separate Transceiver Reference Clock and Core Clock