F-Tile JESD204B Intel® FPGA IP User Guide

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ID 723907
Date 4/23/2024
Public
Document Table of Contents
Document Table of Contents x
1. F-Tile JESD204B IP Quick Reference 2. About the F-Tile JESD204B Intel® FPGA IP 3. Getting Started 4. F-Tile JESD204B IP Functional Description 5. F-Tile JESD204B IP Deterministic Latency Implementation Guidelines 6. F-Tile JESD204B IP Debug Guidelines 7. F-Tile JESD204B Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile JESD204B Intel® FPGA IP User Guide
2. About the F-Tile JESD204B Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. Datapath Modes 2.4. IP Variation 2.5. F-Tile JESD204B IP Configuration 2.6. Channel Bonding 2.7. Performance and Resource Utilization
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Intel® FPGA IP Evaluation Mode 3.4. Upgrading IP Cores 3.5. IP Catalog and Parameter Editor 3.6. Design Walkthrough 3.7. F-Tile JESD204B IP Design Considerations 3.8. F-Tile JESD204B Intel® FPGA IP Parameters 3.9. F-Tile JESD204B IP Component Files
3.6. Design Walkthrough x
3.6.1. Creating a New Quartus® Prime Project 3.6.2. Parameterizing and Generating the IP 3.6.3. Compiling the F-Tile JESD204B IP Core Design 3.6.4. Programming an FPGA Device
3.7. F-Tile JESD204B IP Design Considerations x
3.7.1. Integrating the F-Tile JESD204B IP in Platform Designer 3.7.2. Pin Assignments 3.7.3. Adding External System PLL
4. F-Tile JESD204B IP Functional Description x
4.1. Transmitter 4.2. Receiver 4.3. Operation 4.4. Clocking Scheme 4.5. Reset Scheme 4.6. Signals 4.7. Registers
4.1. Transmitter x
4.1.1. TX Data Link Layer 4.1.2. TX PHY Layer
4.1.1. TX Data Link Layer x
4.1.1.1. TX CGS 4.1.1.2. TX ILAS 4.1.1.3. User Data Phase
4.2. Receiver x
4.2.1. RX Data Link Layer 4.2.2. RX PHY Layer
4.2.1. RX Data Link Layer x
4.2.1.1. RX CGS 4.2.1.2. Frame Synchronization 4.2.1.3. Frame Alignment 4.2.1.4. Lane Alignment 4.2.1.5. ILAS Data 4.2.1.6. Initial Lane Synchronization
4.3. Operation x
4.3.1. Operating Modes 4.3.2. Scrambler/Descrambler 4.3.3. SYNC_N Signal 4.3.4. Link Reinitialization 4.3.5. Link Startup Sequence 4.3.6. Error Reporting Through SYNC_N Signal
4.3.1. Operating Modes x
4.3.1.1. Subclass 0 Operating Mode 4.3.1.2. Subclass 1 Operating Mode 4.3.1.3. Subclass 2 Operating Mode
4.4. Clocking Scheme x
4.4.1. Device Clock 4.4.2. Link Clock 4.4.3. Local MultiFrame Clock 4.4.4. Clock Correlation 4.4.5. System PLL Clock
4.5. Reset Scheme x
4.5.1. Reset Sequence 4.5.2. ADC–FPGA Subsystem Reset Sequence 4.5.3. FPGA–DAC Subsystem Reset Sequence
4.6. Signals x
4.6.1. Transmitter Signals 4.6.2. Receiver Signals
4.7. Registers x
4.7.1. Register Access Type Convention 4.7.2. Register Map and Definition 4.7.3. Transmitter Registers 4.7.4. Receiver Registers
5. F-Tile JESD204B IP Deterministic Latency Implementation Guidelines x
5.1. Constraining Incoming SYSREF Signal 5.2. Programmable RBD Offset 5.3. Programmable LMFC Offset 5.4. Maintaining Deterministic Latency during Link Reinitialization
6. F-Tile JESD204B IP Debug Guidelines x
6.1. Clocking Scheme 6.2. F-Tile JESD204B Parameters 6.3. SPI Programming 6.4. Converter and FPGA Operating Conditions 6.5. Signal Polarity and FPGA Pin Assignment
1. F-Tile JESD204B IP Quick Reference
2. About the F-Tile JESD204B Intel® FPGA IP
3. Getting Started
4. F-Tile JESD204B IP Functional Description
5. F-Tile JESD204B IP Deterministic Latency Implementation Guidelines
6. F-Tile JESD204B IP Debug Guidelines
7. F-Tile JESD204B Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile JESD204B Intel® FPGA IP User Guide

4.4. Clocking Scheme

This section describes the clocking scheme for the F-Tile JESD204B IP core and transceiver.

Table 15.   F-Tile JESD204B IP Core Clocks
Clock Signal Formula Description

TX/RX Device Clock:

pll_ref_clk

PLL selection during IP core generation The PLL reference clock used by the TX Transceiver PLL or RX CDR. This is also the recommended reference clock to the IOPLL Intel FPGA IP core.

TX/RX Link Clock:

txlink_clk

rxlink_clk

Data rate/40 The timing reference for the F-Tile JESD204B IP core. The link clock runs at data rate/40 because the IP core operates in a 40-bit data bus architecture after 8B/10B encoding.

For Subclass 1, to avoid half link clock latency variation, you must supply the device clock at the same frequency as the link clock.

The JESD204B transport layer in the design example requires both the link clock and frame clock to be synchronous.

TX/RX Frame Clock (in design example):

txframe_clk

rxframe_clk

Data rate/(10 × F) The frame clock as per the JESD204B specification. This clock is applicable to the JESD204B transport layer and other upstream devices that run in frame clock such as the PRBS generator/checker or any data processing blocks that run at the same rate as the frame clock.

The JESD204B transport layer in the design example also supports running the frame clock in half rate or quarter rate by using the FRAMECLK_DIV parameter. The JESD204B transport layer requires both the link clock and frame clock to be synchronous. For more information, refer to the F1/F2_FRAMECLK_DIV parameter description and its relationship to the frame clock in the respective F-Tile JESD204B Intel® FPGA IP design example user guides.

TX/RX PHY Clock:

txphy_clk

rxphy_clk

Data rate/40

txphy_clk:
  • TX parallel clock output from the TX transceiver. This clock has the same frequency as txlink_clk signal.
  • This clock is output as an optional port for user if the txlink_clk and txframe_clk signals are operating at the same frequency in Subclass 0 operating mode
rxphy_clk:
  • Transceiver recovered clock signal. This clock is derived from the clock data recovery (CDR) and the frequency depends on the JESD204B IP core data rate.
  • This clock has the same frequency as the rxlink_clk signal.

TX/RX AVS Clock:

jesd204_tx_avs_clk

jesd204_rx_avs_clk

75–125 MHz The configuration clock for the F-Tile JESD204B IP core CSR through the Avalon® memory-mapped interface. This clock is asynchronous to all the clocks.

Transceiver Management Clock:

reconfig_xcvr_clk

100 MHz–250 MHz

 The configuration clock for the transceiver CSR through the Avalon® memory-mapped interface. This clock is exported only when the transceiver dynamic reconfiguration option is enabled.

Tile System PLL Clock:

sysclk

System PLL divide-by 2 Freq (equal or greater than Link Clock Frequency) Generated using system clock PLL. The frequency must be equal or greater than link clock frequency.

Section Content
Device Clock
Link Clock
Local MultiFrame Clock
Clock Correlation
System PLL Clock

Level Two Title