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1. Answers to Top FAQs
2. Intel FPGA Simulation Basics
3. Questa* Intel® FPGA Edition, ModelSim* , and QuestaSim* Simulator Support
4. Synopsys VCS* and VCS MX Support
5. Aldec Active-HDL and Riviera-PRO Support
6. Cadence Xcelium* Parallel Simulator Support
7. Intel® Quartus® Prime Pro Edition User Guide Third-party Simulation Archive
A. Intel® Quartus® Prime Pro Edition User Guides
3.1. Quick Start Example (ModelSim with Verilog)
3.2. Questa* Intel® FPGA Edition, ModelSim, and QuestaSim Simulator Guidelines
3.3. ModelSim Simulation Setup Script Example
3.4. Sourcing ModelSim* or QuestaSim Simulator Setup Scripts
3.5. Unsupported Features
3.6. Questa* Intel® FPGA Edition, ModelSim* , and QuestaSim* Simulator Support Revision History
3.2.1. Using Questa* Intel® FPGA Edition Precompiled Libraries
3.2.2. Passing Parameter Information from Verilog HDL to VHDL
3.2.3. Viewing Simulation Messages
3.2.4. Generating Signal Activity Data for Power Analysis
3.2.5. Viewing Simulation Waveforms
3.2.6. Simulating with Questa* Intel® FPGA Edition Waveform Editor
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4.3. VCS Simulation Setup Script Example
The Intel® Quartus® Prime software can generate a simulation setup script for IP cores in your design. The scripts contain shell commands that compile the required simulation models in the correct order, elaborate the top-level design, and run the simulation for 100 time units by default. You can run these scripts from a Linux command shell.
The scripts for VCS and VCS MX are vcs_setup.sh (for Verilog HDL or SystemVerilog) and vcsmx_setup.sh (combined Verilog HDL and SystemVerilog with VHDL). Read the generated .sh script to see the variables that are available for override when sourcing the script or redefining directly if you edit the script. To set up the simulation for a design, use the command-line to pass variable values to the shell script.
Using Command-line to Pass Simulation Variables
sh vcsmx_setup.sh\
USER_DEFINED_ELAB_OPTIONS=+rad\
USER_DEFINED_SIM_OPTIONS=+vcs+lic+wait
Example Top-Level Simulation Shell Script for VCS-MX
# Run generated script to compile libraries and IP simulation files
# Skip elaboration and simulation of the IP variation
sh ./ip_top_sim/synopsys/vcsmx/vcsmx_setup.sh SKIP_ELAB=1 SKIP_SIM=1 QSYS_SIMDIR="./ip_top_sim"
#Compile top-level testbench that instantiates IP
vlogan -sverilog ./top_testbench.sv
#Elaborate and simulate the top-level design
vcs –lca –t ps <elaboration control options> top_testbench
simv <simulation control options>
Example Top-Level Simulation Shell Script for VCS
# Run script to compile libraries and IP simulation files
sh ./ip_top_sim/synopsys/vcs/vcs_setup.sh TOP_LEVEL_NAME=”top_testbench”\
# Pass VCS elaboration options to compile files and elaborate top-level
passed to the script as the TOP_LEVEL_NAME
USER_DEFINED_ELAB_OPTIONS="top_testbench.sv"\
# Pass in simulation options and run the simulation for specified amount of time.
USER_DEFINED_SIM_OPTIONS=”<simulation control options>