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1. Answers to Top FAQs
2. Intel FPGA Simulation Basics
3. Questa* Intel® FPGA Edition, ModelSim* , and QuestaSim* Simulator Support
4. Synopsys VCS* and VCS MX Support
5. Aldec Active-HDL and Riviera-PRO Support
6. Cadence Xcelium* Parallel Simulator Support
7. Intel® Quartus® Prime Pro Edition User Guide Third-party Simulation Archive
A. Intel® Quartus® Prime Pro Edition User Guides
3.1. Quick Start Example (ModelSim with Verilog)
3.2. Questa* Intel® FPGA Edition, ModelSim, and QuestaSim Simulator Guidelines
3.3. ModelSim Simulation Setup Script Example
3.4. Sourcing ModelSim* or QuestaSim Simulator Setup Scripts
3.5. Unsupported Features
3.6. Questa* Intel® FPGA Edition, ModelSim* , and QuestaSim* Simulator Support Revision History
3.2.1. Using Questa* Intel® FPGA Edition Precompiled Libraries
3.2.2. Passing Parameter Information from Verilog HDL to VHDL
3.2.3. Viewing Simulation Messages
3.2.4. Generating Signal Activity Data for Power Analysis
3.2.5. Viewing Simulation Waveforms
3.2.6. Simulating with Questa* Intel® FPGA Edition Waveform Editor
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5.2. Aldec Active-HDL and Riviera-PRO Guidelines
The following guidelines apply to simulating Intel FPGA designs in the Active-HDL or Riviera-PRO software.
Compiling SystemVerilog Files
If your design includes multiple SystemVerilog files, you must compile the System Verilog files together with a single alog command.
If you have Verilog files and SystemVerilog files in your design, you must first compile the Verilog files, and then compile only the SystemVerilog files in the single alog command.