ID
683870
Date
4/13/2022
Public
Visible to Intel only — GUID: faq
Ixiasoft
1. Answers to Top FAQs
2. Intel FPGA Simulation Basics
3. Questa* Intel® FPGA Edition, ModelSim* , and QuestaSim* Simulator Support
4. Synopsys VCS* and VCS MX Support
5. Aldec Active-HDL and Riviera-PRO Support
6. Cadence Xcelium* Parallel Simulator Support
7. Intel® Quartus® Prime Pro Edition User Guide Third-party Simulation Archive
A. Intel® Quartus® Prime Pro Edition User Guides
3.1. Quick Start Example (ModelSim with Verilog)
3.2. Questa* Intel® FPGA Edition, ModelSim, and QuestaSim Simulator Guidelines
3.3. ModelSim Simulation Setup Script Example
3.4. Sourcing ModelSim* or QuestaSim Simulator Setup Scripts
3.5. Unsupported Features
3.6. Questa* Intel® FPGA Edition, ModelSim* , and QuestaSim* Simulator Support Revision History
3.2.1. Using Questa* Intel® FPGA Edition Precompiled Libraries
3.2.2. Passing Parameter Information from Verilog HDL to VHDL
3.2.3. Viewing Simulation Messages
3.2.4. Generating Signal Activity Data for Power Analysis
3.2.5. Viewing Simulation Waveforms
3.2.6. Simulating with Questa* Intel® FPGA Edition Waveform Editor
Visible to Intel only — GUID: faq
Ixiasoft
1. Answers to Top FAQs
Updated for: |
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Intel® Quartus® Prime Design Suite 22.1 |
What’s new in this version? |
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What is simulation? |
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Does Quartus include a simulator? |
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Does Quartus support my simulator? |
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What do I need for simulation? |
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How do I simulate my IP? |
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Where are my simulator files? |
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What are the known issues and limitations? |
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Do you have training on simulation? |