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1. Answers to Top FAQs
2. Intel FPGA Simulation Basics
3. Questa* Intel® FPGA Edition, ModelSim* , and QuestaSim* Simulator Support
4. Synopsys VCS* and VCS MX Support
5. Aldec Active-HDL and Riviera-PRO Support
6. Cadence Xcelium* Parallel Simulator Support
7. Intel® Quartus® Prime Pro Edition User Guide Third-party Simulation Archive
A. Intel® Quartus® Prime Pro Edition User Guides
3.1. Quick Start Example (ModelSim with Verilog)
3.2. Questa* Intel® FPGA Edition, ModelSim, and QuestaSim Simulator Guidelines
3.3. ModelSim Simulation Setup Script Example
3.4. Sourcing ModelSim* or QuestaSim Simulator Setup Scripts
3.5. Unsupported Features
3.6. Questa* Intel® FPGA Edition, ModelSim* , and QuestaSim* Simulator Support Revision History
3.2.1. Using Questa* Intel® FPGA Edition Precompiled Libraries
3.2.2. Passing Parameter Information from Verilog HDL to VHDL
3.2.3. Viewing Simulation Messages
3.2.4. Generating Signal Activity Data for Power Analysis
3.2.5. Viewing Simulation Waveforms
3.2.6. Simulating with Questa* Intel® FPGA Edition Waveform Editor
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5.1. Quick Start Example (Active-HDL VHDL)
You can adapt the following RTL simulation example to get started quickly with Active-HDL:
- To specify your EDA simulator and executable path, type the following Tcl package command in the Intel® Quartus® Prime tcl shell window:
set_user_option -name EDA_TOOL_PATH_ACTIVEHDL <Active HDL executable path>set_global_assignment -name EDA_SIMULATION_TOOL "Active-HDL (VHDL)"
- Compile simulation model libraries using one of the following methods:
- To automatically compile all required simulation model libraries for your design in your supported simulator, click Tools > Launch Simulation Library Compiler. Specify options for your simulation tool, language, target device family, and output location, and then click OK.
- Compile Intel FPGA simulation models manually:
vlib <library1> <altera_library1> vcom -strict93 -dbg -work <library1> <lib1_component/pack.vhd> \ <lib1.vhd>
Use the compiled simulation model libraries during simulation of your design. Refer to your EDA simulator's documentation for information about running simulation.
- Open the Active-HDL simulator.
- Create and open the workspace:
createdesign <workspace name> <workspace path> opendesign -a <workspace name>.adf
- Create the work library and compile the netlist and testbench files:
vlib work vcom -strict93 -dbg -work work <output netlist> <testbench file>
- Load the design:
vsim +access+r -t 1ps +transport_int_delays +transport_path_delays \ -L work -L <lib1> -L <lib2> work.<testbench module name>
- Run the simulation in the Active-HDL simulator.