Intel® Quartus® Prime Pro Edition User Guide: Third-party Simulation

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ID 683870
Date 4/13/2022
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Intel FPGA Simulation Basics 3. Questa* Intel® FPGA Edition, ModelSim* , and QuestaSim* Simulator Support 4. Synopsys VCS* and VCS MX Support 5. Aldec Active-HDL and Riviera-PRO Support 6. Cadence Xcelium* Parallel Simulator Support 7. Intel® Quartus® Prime Pro Edition User Guide Third-party Simulation Archive A. Intel® Quartus® Prime Pro Edition User Guides
2. Intel FPGA Simulation Basics x
2.1. Supported Simulators 2.2. Supported Simulation Levels 2.3. Supported Hardware Description Languages 2.4. Supported Simulation Flows 2.5. Preparing for Simulation 2.6. Running a Simulation (Custom Flow) 2.7. Intel FPGA Simulation Basics Revision History
2.5. Preparing for Simulation x
2.5.1. Compiling Simulation Model Libraries 2.5.2. Using The EDA Netlist Writer 2.5.3. Simulating Intel® FPGA IP Cores
2.5.3. Simulating Intel® FPGA IP Cores x
2.5.3.1. Generating IP Simulation Files 2.5.3.2. Scripting IP Simulation
2.5.3.2. Scripting IP Simulation x
2.5.3.2.1. Generating a Combined Simulator Setup Script 2.5.3.2.2. Incorporating Simulator Setup Scripts from the Generated Template
3. Questa* Intel® FPGA Edition, ModelSim* , and QuestaSim* Simulator Support x
3.1. Quick Start Example (ModelSim with Verilog) 3.2. Questa* Intel® FPGA Edition, ModelSim, and QuestaSim Simulator Guidelines 3.3. ModelSim Simulation Setup Script Example 3.4. Sourcing ModelSim* or QuestaSim Simulator Setup Scripts 3.5. Unsupported Features 3.6. Questa* Intel® FPGA Edition, ModelSim* , and QuestaSim* Simulator Support Revision History
3.2. Questa* Intel® FPGA Edition, ModelSim, and QuestaSim Simulator Guidelines x
3.2.1. Using Questa* Intel® FPGA Edition Precompiled Libraries 3.2.2. Passing Parameter Information from Verilog HDL to VHDL 3.2.3. Viewing Simulation Messages 3.2.4. Generating Signal Activity Data for Power Analysis 3.2.5. Viewing Simulation Waveforms 3.2.6. Simulating with Questa* Intel® FPGA Edition Waveform Editor
3.2.4. Generating Signal Activity Data for Power Analysis x
3.2.4.1. Generating Standard Delay Output for Power Analysis
4. Synopsys VCS* and VCS MX Support x
4.1. Quick Start Example (VCS with Verilog) 4.2. VCS and VCS MX Guidelines 4.3. VCS Simulation Setup Script Example 4.4. Sourcing Synopsys VCS* MX Simulator Setup Scripts 4.5. Sourcing Synopsys VCS* Simulator Setup Scripts 4.6. Synopsys VCS* and VCS MX Support Revision History
5. Aldec Active-HDL and Riviera-PRO Support x
5.1. Quick Start Example (Active-HDL VHDL) 5.2. Aldec Active-HDL and Riviera-PRO Guidelines 5.3. Using Simulation Setup Scripts 5.4. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts 5.5. Aldec Active-HDL* and Riviera-PRO * Support Revision History
6. Cadence Xcelium* Parallel Simulator Support x
6.1. Using the Command-Line Interface 6.2. Sourcing Cadence Xcelium* Simulator Setup Scripts 6.3. Cadence Xcelium* Parallel Simulator Support Revision History
1. Answers to Top FAQs
2. Intel FPGA Simulation Basics
3. Questa* Intel® FPGA Edition, ModelSim* , and QuestaSim* Simulator Support
4. Synopsys VCS* and VCS MX Support
5. Aldec Active-HDL and Riviera-PRO Support
6. Cadence Xcelium* Parallel Simulator Support
7. Intel® Quartus® Prime Pro Edition User Guide Third-party Simulation Archive
A. Intel® Quartus® Prime Pro Edition User Guides

2.3. Supported Hardware Description Languages

The Intel® Quartus® Prime software provides the following hardware description language (HDL) support for EDA simulators.
Table 3.  HDL Support
Language Support Description

VHDL

  • For VHDL RTL simulation, you compile design files and testbench directly in your simulator. For all supported simulators other than Questa* Intel® FPGA Edition, you must also compile simulation models from the Intel FPGA simulation libraries and simulation models for the IP cores in your design.
  • For gate-level simulation, the Intel® Quartus® Prime EDA Netlist Writer generates a synthesized design netlist VHDL Output File (.vho). You compile the .vho in your simulator.
  • To simulate the model in a VHDL design, you may require a simulator that is capable of VHDL/Verilog HDL co-simulation.

Verilog /SystemVerilog

  • For RTL simulation in Verilog HDL or SystemVerilog, you compile your design files in your simulator. For all supported simulators other than Questa* Intel® FPGA Edition, you must also compile simulation models from the Intel FPGA simulation libraries and simulation models for the IP cores in your design.
  • For gate-level simulation, the EDA Netlist Writer generates a synthesized design netlist Verilog Output File (.vo). Compile the .vo in your simulator.

Mixed HDL

  • If your design is a mix of VHDL, Verilog HDL, and SystemVerilog files, you must use a mixed language simulator. Choose the most convenient supported language for generation of Intel FPGA IP cores in your design.
  • The Questa* Intel® FPGA Edition software supports native, mixed-language (VHDL/Verilog HDL/SystemVerilog) co-simulation of plain text HDL.

    If you have a VHDL-only simulator and need to simulate Verilog HDL modules and IP cores, you can either acquire a mixed-language simulator license from the simulator vendor, or use the Questa* Intel® FPGA Edition simulator.

Schematic

  • To perform RTL simulation of the schematic, you must convert the schematic to HDL format and run RTL simulation on the HDL. The Intel® Quartus® Prime Pro Edition software cannot perform schematic conversion.
  • To perform post-synthesis or post-fit simulation, you must first compile the schematic in the Intel® Quartus® Prime software, generate a gate-level simulation netlist, and perform simulation on the netlist.
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