Intel® Quartus® Prime Pro Edition User Guide: Third-party Simulation

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ID 683870
Date 4/13/2022
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Intel FPGA Simulation Basics 3. Questa* Intel® FPGA Edition, ModelSim* , and QuestaSim* Simulator Support 4. Synopsys VCS* and VCS MX Support 5. Aldec Active-HDL and Riviera-PRO Support 6. Cadence Xcelium* Parallel Simulator Support 7. Intel® Quartus® Prime Pro Edition User Guide Third-party Simulation Archive A. Intel® Quartus® Prime Pro Edition User Guides
2. Intel FPGA Simulation Basics x
2.1. Supported Simulators 2.2. Supported Simulation Levels 2.3. Supported Hardware Description Languages 2.4. Supported Simulation Flows 2.5. Preparing for Simulation 2.6. Running a Simulation (Custom Flow) 2.7. Intel FPGA Simulation Basics Revision History
2.5. Preparing for Simulation x
2.5.1. Compiling Simulation Model Libraries 2.5.2. Using The EDA Netlist Writer 2.5.3. Simulating Intel® FPGA IP Cores
2.5.3. Simulating Intel® FPGA IP Cores x
2.5.3.1. Generating IP Simulation Files 2.5.3.2. Scripting IP Simulation
2.5.3.2. Scripting IP Simulation x
2.5.3.2.1. Generating a Combined Simulator Setup Script 2.5.3.2.2. Incorporating Simulator Setup Scripts from the Generated Template
3. Questa* Intel® FPGA Edition, ModelSim* , and QuestaSim* Simulator Support x
3.1. Quick Start Example (ModelSim with Verilog) 3.2. Questa* Intel® FPGA Edition, ModelSim, and QuestaSim Simulator Guidelines 3.3. ModelSim Simulation Setup Script Example 3.4. Sourcing ModelSim* or QuestaSim Simulator Setup Scripts 3.5. Unsupported Features 3.6. Questa* Intel® FPGA Edition, ModelSim* , and QuestaSim* Simulator Support Revision History
3.2. Questa* Intel® FPGA Edition, ModelSim, and QuestaSim Simulator Guidelines x
3.2.1. Using Questa* Intel® FPGA Edition Precompiled Libraries 3.2.2. Passing Parameter Information from Verilog HDL to VHDL 3.2.3. Viewing Simulation Messages 3.2.4. Generating Signal Activity Data for Power Analysis 3.2.5. Viewing Simulation Waveforms 3.2.6. Simulating with Questa* Intel® FPGA Edition Waveform Editor
3.2.4. Generating Signal Activity Data for Power Analysis x
3.2.4.1. Generating Standard Delay Output for Power Analysis
4. Synopsys VCS* and VCS MX Support x
4.1. Quick Start Example (VCS with Verilog) 4.2. VCS and VCS MX Guidelines 4.3. VCS Simulation Setup Script Example 4.4. Sourcing Synopsys VCS* MX Simulator Setup Scripts 4.5. Sourcing Synopsys VCS* Simulator Setup Scripts 4.6. Synopsys VCS* and VCS MX Support Revision History
5. Aldec Active-HDL and Riviera-PRO Support x
5.1. Quick Start Example (Active-HDL VHDL) 5.2. Aldec Active-HDL and Riviera-PRO Guidelines 5.3. Using Simulation Setup Scripts 5.4. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts 5.5. Aldec Active-HDL* and Riviera-PRO * Support Revision History
6. Cadence Xcelium* Parallel Simulator Support x
6.1. Using the Command-Line Interface 6.2. Sourcing Cadence Xcelium* Simulator Setup Scripts 6.3. Cadence Xcelium* Parallel Simulator Support Revision History
1. Answers to Top FAQs
2. Intel FPGA Simulation Basics
3. Questa* Intel® FPGA Edition, ModelSim* , and QuestaSim* Simulator Support
4. Synopsys VCS* and VCS MX Support
5. Aldec Active-HDL and Riviera-PRO Support
6. Cadence Xcelium* Parallel Simulator Support
7. Intel® Quartus® Prime Pro Edition User Guide Third-party Simulation Archive
A. Intel® Quartus® Prime Pro Edition User Guides

3.2.4.1. Generating Standard Delay Output for Power Analysis

To improve accuracy of power analysis, you can generate a Standard Delay Output (.sdo) file that includes back-annotated delay estimates for ModelSim* simulation. ModelSim* simulation can then output a more accurate .vcd for use as power analysis input. You must run Fitter (Finalize) before generating the .sdo.
Using an SDO in Power Analysis
  1. Click Assignments > Settings > EDA Tool Settings > Simulation. In Tool name select ModelSim* and Verilog for Format for output netlist.
  2. Click More EDA Netlist Writer Settings. Set Enable SDO Generation for Power Estimation to On. Set Generate Power Estimate Scripts to ALL_NODES.
    Figure 8. More EDA Netlist Writer Settings
  3. To run the Fitter, click Processing > Start > Start Fitter (Finalize).
  4. Create a representative testbench (.vt) that exercises the design functions appropriately.
  5. To specify the appropriate hierarchy level for signals in the output .vcd, add the following line to the project .qsf file: 
    set_global_assignment -name EDA_TEST_BENCH_DESIGN_INSTANCE_NAME 
     <DUT instance path> -section_id eda_simulation
    3
  6. After Fitter processing is complete, click Processing > Start > Start EDA Netlist Writer. EDA Netlist Writer generates the following files in /<project>/simulation/modelsim/power/:
    • <project>.vo (contains a reference to the .sdo file by default)
    • <project>_dump_all_vcd_nodes.tcl—specifies nodes to save in .vcd
    • <project>_v.sdo—back-annotated delay estimates
  7. Create a ModelSim* script (.do) to load the design and testbench, start ModelSim* , and then source the .do script.
  8. To specify the signals ModelSim* includes in the .vcd file, source *_dump_all_vcd_nodes.tcl in ModelSim* .
  9. To generate the .vcd file, simulate the test bench and netlist in ModelSim* . The .vcd file generates according to your specifications.
  10. Specify the .vcd as an input to power analysis, as Generating Signal Activity Data for Power Analysis describes.
    Note: The EDA Netlist Writer currently supports .sdo file generation only for Verilog .vo simulation in the ModelSim* simulator (not Questa* Intel® FPGA Edition) for Intel® Stratix® 10 designs. The EDA Netlist Writer does not currently support .sdo file generation for any other simulator or device family.
3 Specify the full hierarchical path in the testbench, not just the instance name. For example, specify a|b|c, not just c.
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