Intel® Quartus® Prime Pro Edition User Guide: Third-party Simulation

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ID 683870
Date 4/13/2022
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Intel FPGA Simulation Basics 3. Questa* Intel® FPGA Edition, ModelSim* , and QuestaSim* Simulator Support 4. Synopsys VCS* and VCS MX Support 5. Aldec Active-HDL and Riviera-PRO Support 6. Cadence Xcelium* Parallel Simulator Support 7. Intel® Quartus® Prime Pro Edition User Guide Third-party Simulation Archive A. Intel® Quartus® Prime Pro Edition User Guides
2. Intel FPGA Simulation Basics x
2.1. Supported Simulators 2.2. Supported Simulation Levels 2.3. Supported Hardware Description Languages 2.4. Supported Simulation Flows 2.5. Preparing for Simulation 2.6. Running a Simulation (Custom Flow) 2.7. Intel FPGA Simulation Basics Revision History
2.5. Preparing for Simulation x
2.5.1. Compiling Simulation Model Libraries 2.5.2. Using The EDA Netlist Writer --simulation --tool= --format= --resynthesis --power --partition= --exclude_sub_partitions --module_name 2.5.3. Simulating Intel® FPGA IP Cores
2.5.3. Simulating Intel® FPGA IP Cores x
2.5.3.1. Generating IP Simulation Files 2.5.3.2. Scripting IP Simulation
2.5.3.2. Scripting IP Simulation x
2.5.3.2.1. Generating a Combined Simulator Setup Script 2.5.3.2.2. Incorporating Simulator Setup Scripts from the Generated Template
3. Questa* Intel® FPGA Edition, ModelSim* , and QuestaSim* Simulator Support x
3.1. Quick Start Example (ModelSim with Verilog) 3.2. Questa* Intel® FPGA Edition, ModelSim, and QuestaSim Simulator Guidelines 3.3. ModelSim Simulation Setup Script Example 3.4. Sourcing ModelSim* or QuestaSim Simulator Setup Scripts 3.5. Unsupported Features 3.6. Questa* Intel® FPGA Edition, ModelSim* , and QuestaSim* Simulator Support Revision History
3.2. Questa* Intel® FPGA Edition, ModelSim, and QuestaSim Simulator Guidelines x
3.2.1. Using Questa* Intel® FPGA Edition Precompiled Libraries 3.2.2. Passing Parameter Information from Verilog HDL to VHDL 3.2.3. Viewing Simulation Messages 3.2.4. Generating Signal Activity Data for Power Analysis 3.2.5. Viewing Simulation Waveforms 3.2.6. Simulating with Questa* Intel® FPGA Edition Waveform Editor
3.2.4. Generating Signal Activity Data for Power Analysis x
3.2.4.1. Generating Standard Delay Output for Power Analysis
4. Synopsys VCS* and VCS MX Support x
4.1. Quick Start Example (VCS with Verilog) 4.2. VCS and VCS MX Guidelines 4.3. VCS Simulation Setup Script Example 4.4. Sourcing Synopsys VCS* MX Simulator Setup Scripts 4.5. Sourcing Synopsys VCS* Simulator Setup Scripts 4.6. Synopsys VCS* and VCS MX Support Revision History
5. Aldec Active-HDL and Riviera-PRO Support x
5.1. Quick Start Example (Active-HDL VHDL) 5.2. Aldec Active-HDL and Riviera-PRO Guidelines 5.3. Using Simulation Setup Scripts 5.4. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts 5.5. Aldec Active-HDL* and Riviera-PRO * Support Revision History
6. Cadence Xcelium* Parallel Simulator Support x
6.1. Using the Command-Line Interface 6.2. Sourcing Cadence Xcelium* Simulator Setup Scripts 6.3. Cadence Xcelium* Parallel Simulator Support Revision History
1. Answers to Top FAQs
2. Intel FPGA Simulation Basics
3. Questa* Intel® FPGA Edition, ModelSim* , and QuestaSim* Simulator Support
4. Synopsys VCS* and VCS MX Support
5. Aldec Active-HDL and Riviera-PRO Support
6. Cadence Xcelium* Parallel Simulator Support
7. Intel® Quartus® Prime Pro Edition User Guide Third-party Simulation Archive
A. Intel® Quartus® Prime Pro Edition User Guides

2.5.2. Using The EDA Netlist Writer

The Intel® Quartus® Prime EDA Netlist Writer (quartus_eda on the command line) allows you to write gate-level (technology mapped) netlists for simulation and other applications. Using simulation of gate-level netlists as the main method of testing and validation is not recommended. Gate level simulation is slower than RTL simulation and it is harder to debug because of the remapping of nodes and names.

The EDA netlist writer supports the following design port types. Your design ports must be of these types to generate a .vo or .vho netlist for simulation:

  • Single-bit signal types
  • One-dimensional arrays
  • Two-dimensional arrays

The EDA Netlist Writer does not support complex data types, such as enums, stucts, unions, or interfaces, at the external boundary of the design or the partition that it produces.

The EDA Netlist Writer can produce netlists after synthesis and after the completion of the Fitter, the synthesized, and final snapshot respectively. The EDA Netlist Writer supports output of Verilog (.vo) and VHDL (.vho) netlists. The EDA Netlist Writer can also produce Verilog Quartus Map (.vqm) netlists for resynthesis.

Start the EDA Netlist Writer from the Processing menu, or from the command line using quartus_eda, followed by the set of options to specify the type of netlist to produce.

--simulation

The simulation flag specifies that quartus_eda creates a Verilog (.vo) or VHDL (.vho) gate-level netlist, for simulation by one of the supported simulators. This option requires you to also specify the target tool and format for the simulation.

--tool=<modelsim|questa_oem|vcs|vcs_mx|xcelium|rivierapro|activehdl|verilogxl>

This option specifies that quartus_eda writes out a netlist for the specified third-party EDA tool. You can choose the third-party EDA tool from one of the three categories of available tools: simulation, timing analysis, or board level design and analysis.

This option overrides the settings specified in the Intel® Quartus® Prime Settings File (.qsf). Specify both the tool name and format to generate a netlist.

--format=<vhdl|verilog|ibis (when using with –board_signal_integrity flag)>

The --format option specifies whether the simulation option produces a Verilog or VHDL gate-level netlist.

--resynthesis

The --resynthesis flag specifies that quartus_eda creates a Verilog Quartus Map (.vqm) netlist. The software can resynthesize the netlist as an RTL input, from the gate-level netlist. Only use this option with partitions containing core logic only, not periphery. The sub-option is a flag only and takes no arguments.

--power

The --power flag specifies that quartus_eda generates a standard delay format output (.sdo) file. You can use this file in power analysis, but the file is not a fully accurate timing simulation. Currently this option is only supported for Verilog HDL simulations in the ModelSim* simulator.

--partition=<partition name>

The --partition selects an individual partition as the netlist output. For no partition argument, the software writes the entire design out to a single file. The partition argument takes a name of a partition in the design.

You can use the --partition option with the --simulation (.vo, .vho) and --resynthesis (.vqm) output.

--exclude_sub_partitions

The --exclude_sub_partitions flag limits the output to the netlist of this partition only. This flag is only valid when you use the --partition option, this flag outputs the netlist belonging to the partition you specify. The software instantiates subpartitions as module instances in the netlist. The sub-option is a flag only and takes no arguments.

When you specify the --exclude_sub_partitions flag, the software only writes out the contents of the selected partition. Each call of quartus_eda writes one netlist. If you write out the design one partition at a time, using the exclude_sub_partitions flag, you need to call quartus_eda for each partition in the design including the root.

You can specify the root_partition as the partition name in the --partition option to get the top level partition, which is useful when using the --exclude_sub_partitions flag.

--module_name

The --module_name option allows you to rename a partition name in the generated netlist file. By default, the software uses the partition name as the module name in the netlist file. This option is only valid when you use the --partition option. You can rename any module using --module_name=abc=xyz. The generated file names format is: <revision>.<partition name>.<vo or vho>. By default, the Intel® Quartus® Prime software writes the netlist file to the simulation directory (for example, simulation/questa), unless you specify an output_directory (using a command line option or .qsf assignment).

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