Quartus® Prime Pro Edition User Guide: Debug Tools

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ID 683819
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. System Debugging Tools Overview 2. Design Debugging with the Signal Tap Logic Analyzer 3. Quick Design Verification with Signal Probe 4. In-System Debugging Using External Logic Analyzers 5. In-System Modification of Memory and Constants 6. Design Debugging Using In-System Sources and Probes 7. Analyzing and Debugging Designs with System Console 8. Quartus® Prime Pro Edition User Guide Debug Tools Archives A. Quartus® Prime Pro Edition User Guides
1. System Debugging Tools Overview x
1.1. System Debugging Tools Portfolio 1.2. Tools for Monitoring RTL Nodes 1.3. Stimulus-Capable Tools 1.4. Virtual JTAG Interface Intel® FPGA IP 1.5. System-Level Debug Fabric 1.6. SLD JTAG Bridge 1.7. Partial Reconfiguration Design Debugging 1.8. Preserving Signals for Debugging 1.9. System Debugging Tools Overview Revision History
1.1. System Debugging Tools Portfolio x
1.1.1. System Debugging Tools Comparison 1.1.2. Suggested Tools for Common Debugging Requirements 1.1.3. Debugging Ecosystem
1.2. Tools for Monitoring RTL Nodes x
1.2.1. Resource Usage 1.2.2. Pin Usage 1.2.3. Usability Enhancements
1.2.1. Resource Usage x
1.2.1.1. Overhead Logic
1.2.1.1. Overhead Logic x
1.2.1.1.1. For Signal Tap Logic Analyzer 1.2.1.1.2. For Signal Probe 1.2.1.1.3. For Logic Analyzer Interface
1.2.2. Pin Usage x
1.2.2.1. For Signal Tap Logic Analyzer 1.2.2.2. For Signal Probe 1.2.2.3. For Logic Analyzer Interface
1.2.3. Usability Enhancements x
1.2.3.1. Incremental Routing 1.2.3.2. Automation Via Scripting
1.3. Stimulus-Capable Tools x
1.3.1. In-System Sources and Probes 1.3.2. In-System Memory Content Editor 1.3.3. System Console
1.3.1. In-System Sources and Probes x
1.3.1.1. Push Button Functionality
1.3.2. In-System Memory Content Editor x
1.3.2.1. Generate Test Vectors
1.3.3. System Console x
1.3.3.1. Test Signal Integrity 1.3.3.2. Board Bring-Up and Verification 1.3.3.3. Debug with Available Toolkits
1.6. SLD JTAG Bridge x
1.6.1. SLD JTAG Bridge Index 1.6.2. Instantiating the SLD JTAG Bridge Agent 1.6.3. Instantiating the SLD JTAG Bridge Host
1.7. Partial Reconfiguration Design Debugging x
1.7.1. Debug Fabric for Partial Reconfiguration Designs
1.7.1. Debug Fabric for Partial Reconfiguration Designs x
1.7.1.1. Generation of PR Debug Infrastructure
1.8. Preserving Signals for Debugging x
1.8.1. Preserve for Debug Overview 1.8.2. Marking Signals for Debug
1.8.2. Marking Signals for Debug x
1.8.2.1. Step 1: Enabling Preserve for Debug 1.8.2.2. Step 2: Implement Preserve for Debug Assignments 1.8.2.3. Step 3: Locate and Report Preserve for Debug Nodes
1.8.2.1. Step 1: Enabling Preserve for Debug x
1.8.2.1.1. Enabling Preserve for Debug In Project Settings 1.8.2.1.2. Enabling Preserve for Debug at Instance Level
1.8.2.2. Step 2: Implement Preserve for Debug Assignments x
1.8.2.2.1. HDL Implementation 1.8.2.2.2. Quartus® Prime Settings Implementation
1.8.2.3. Step 3: Locate and Report Preserve for Debug Nodes x
1.8.2.3.1. Locating Preserve for Debug Nodes 1.8.2.3.2. Reporting Preserve for Debug Nodes
2. Design Debugging with the Signal Tap Logic Analyzer x
2.1. Signal Tap Logic Analyzer Introduction 2.2. Signal Tap Debugging Flow 2.3. Step 1: Add the Signal Tap Logic Analyzer to the Project 2.4. Step 2: Configure the Signal Tap Logic Analyzer 2.5. Step 3: Compile the Design and Signal Tap Instances 2.6. Step 4: Program the Target Hardware 2.7. Step 5: Run the Signal Tap Logic Analyzer 2.8. Step 6: Analyze Signal Tap Captured Data 2.9. Simulation-Aware Signal Tap 2.10. Other Signal Tap Debugging Flows 2.11. Signal Tap Logic Analyzer Design Examples 2.12. Custom State-Based Triggering Flow Examples 2.13. Signal Tap File Templates 2.14. Running the Standalone Version of Signal Tap 2.15. Signal Tap Scripting Support 2.16. Merge Multiple Signal Tap files 2.17. Signal Tap File Version Compatibility 2.18. Design Debugging with the Signal Tap Logic Analyzer Revision History
2.1. Signal Tap Logic Analyzer Introduction x
2.1.1. Signal Tap Hardware and Software Requirements
2.3. Step 1: Add the Signal Tap Logic Analyzer to the Project x
2.3.1. Creating a Signal Tap Instance with the Signal Tap GUI 2.3.2. Creating a Signal Tap Instance by HDL Instantiation
2.3.1. Creating a Signal Tap Instance with the Signal Tap GUI x
2.3.1.1. Managing Signal Tap Instances
2.3.2. Creating a Signal Tap Instance by HDL Instantiation x
2.3.2.1. Signal Tap Intel® FPGA IP Parameters
2.4. Step 2: Configure the Signal Tap Logic Analyzer x
2.4.1. Preserving Signals for Monitoring and Debugging 2.4.2. Preventing Changes that Require Full Recompilation 2.4.3. Specifying the Clock, Sample Depth, and RAM Type 2.4.4. Specifying the Buffer Acquisition Mode 2.4.5. Adding Signals to the Signal Tap Logic Analyzer 2.4.6. Defining Trigger Conditions 2.4.7. Specifying Pipeline Settings 2.4.8. Filtering Relevant Samples
2.4.4. Specifying the Buffer Acquisition Mode x
2.4.4.1. Non-Segmented Buffer 2.4.4.2. Segmented Buffer
2.4.5. Adding Signals to the Signal Tap Logic Analyzer x
2.4.5.1. Adding Pre-Synthesis or Post-Fit Nodes 2.4.5.2. Adding Simulation-Aware Signal Tap Nodes 2.4.5.3. Adding Nios® II Processor Signals with a Plug-In 2.4.5.4. Signals Unavailable for Signal Tap Debugging 2.4.5.5. Organizing Signals in the Signal Tap Logic Analyzer
2.4.5.2. Adding Simulation-Aware Signal Tap Nodes x
2.4.5.2.1. Add Simulator-Aware Node Finder Settings
2.4.6. Defining Trigger Conditions x
2.4.6.1. Basic Trigger Conditions 2.4.6.2. Nested Trigger Conditions 2.4.6.3. Comparison Trigger Conditions 2.4.6.4. Advanced Trigger Conditions 2.4.6.5. Custom Trigger HDL Object 2.4.6.6. Specify Trigger Position 2.4.6.7. Power-Up Triggers 2.4.6.8. External Triggers 2.4.6.9. Trigger Condition Flow Control 2.4.6.10. Sequential Triggering 2.4.6.11. State-Based Triggering 2.4.6.12. Trigger Lock Mode
2.4.6.3. Comparison Trigger Conditions x
2.4.6.3.1. Specifying the Comparison Trigger Conditions
2.4.6.4. Advanced Trigger Conditions x
2.4.6.4.1. Examples of Advanced Triggering Expressions
2.4.6.5. Custom Trigger HDL Object x
2.4.6.5.1. Using the Custom Trigger HDL Object 2.4.6.5.2. Required Inputs and Outputs of Custom Trigger HDL Module 2.4.6.5.3. Custom Trigger HDL Module Properties
2.4.6.6. Specify Trigger Position x
2.4.6.6.1. Post-fill Count
2.4.6.7. Power-Up Triggers x
2.4.6.7.1. Enabling a Power-Up Trigger 2.4.6.7.2. Configuring Power-Up Trigger Conditions 2.4.6.7.3. Managing Signal Tap Instances with Run-Time and Power-Up Trigger Conditions
2.4.6.10. Sequential Triggering x
2.4.6.10.1. Configuring the Sequential Triggering Flow
2.4.6.11. State-Based Triggering x
2.4.6.11.1. State-Based Triggering Flow Tab 2.4.6.11.2. State Machine Pane 2.4.6.11.3. Resources Pane 2.4.6.11.4. State Diagram Pane 2.4.6.11.5. Signal Tap Trigger Flow Description Language 2.4.6.11.6. State-Based Storage Qualifier Feature
2.4.6.11.5. Signal Tap Trigger Flow Description Language x
2.4.6.11.5.1. <state_label> 2.4.6.11.5.2. <boolean_expression> 2.4.6.11.5.3. <action_list> 2.4.6.11.5.4. Trigger that Skips Clock Cycles after Hitting Condition 2.4.6.11.5.5. Storage Qualification with Post-Fill Count Value Less than m 2.4.6.11.5.6. Resource Manipulation Action 2.4.6.11.5.7. Buffer Control Actions 2.4.6.11.5.8. State Transition Action
2.4.6.11.6. State-Based Storage Qualifier Feature x
2.4.6.11.6.1. Storage Qualification Feature for the State-Based Trigger Flow
2.4.8. Filtering Relevant Samples x
2.4.8.1. Input Port Mode 2.4.8.2. Transitional Mode 2.4.8.3. Conditional Mode 2.4.8.4. Start/Stop Mode 2.4.8.5. State-Based Mode 2.4.8.6. Showing Data Discontinuities 2.4.8.7. Disable the Storage Qualifier
2.5. Step 3: Compile the Design and Signal Tap Instances x
2.5.1. Recompiling Only Signal Tap Changes 2.5.2. Timing Preservation 2.5.3. Performance and Resource Considerations
2.5.3. Performance and Resource Considerations x
2.5.3.1. Increasing Signal Tap Logic Performance 2.5.3.2. Reducing Signal Tap Device Resources
2.6. Step 4: Program the Target Hardware x
2.6.1. Ensure Compatibility Between .stp and .sof Files
2.7. Step 5: Run the Signal Tap Logic Analyzer x
2.7.1. Changing the Post-Fit Signal Tap Target Nodes 2.7.2. Runtime Reconfigurable Options 2.7.3. Signal Tap Status Messages
2.8. Step 6: Analyze Signal Tap Captured Data x
2.8.1. Viewing Capture Data Using Segmented Buffers 2.8.2. Viewing Data with Different Acquisition Modes 2.8.3. Creating Mnemonics for Bit Patterns 2.8.4. Locating a Node in the Design 2.8.5. Saving Captured Signal Tap Data 2.8.6. Exporting Captured Signal Tap Data 2.8.7. Creating a Signal Tap List File
2.8.2. Viewing Data with Different Acquisition Modes x
2.8.2.1. Continuous Mode and a Storage Qualifier Examples
2.8.3. Creating Mnemonics for Bit Patterns x
2.8.3.1. Adding Mnemonics with a Plug-In
2.9. Simulation-Aware Signal Tap x
2.9.1. Generating a Simulation Testbench from Signal Tap Data 2.9.2. Create Simulation Testbench Dialog Box Settings
2.10. Other Signal Tap Debugging Flows x
2.10.1. Managing Multiple Signal Tap Configurations 2.10.2. Debugging Partial Reconfiguration Designs with Signal Tap 2.10.3. Debugging Block-Based Designs with Signal Tap 2.10.4. Debugging Devices that use Configuration Bitstream Security 2.10.5. Signal Tap Data Capture with the MATLAB* MEX Function
2.10.1. Managing Multiple Signal Tap Configurations x
2.10.1.1. Data Log Pane 2.10.1.2. SOF Manager
2.10.2. Debugging Partial Reconfiguration Designs with Signal Tap x
2.10.2.1. Signal Tap Guidelines for PR Designs 2.10.2.2. PR Design Setup for Signal Tap Debug 2.10.2.3. Performing Data Acquisition in a PR design
2.10.2.2. PR Design Setup for Signal Tap Debug x
2.10.2.2.1. Preparing the Static Region for Signal Tap Debugging 2.10.2.2.2. Preparing the Base Revision for Signal Tap Debugging 2.10.2.2.3. Preparing PR Personas for Signal Tap Debugging
2.10.3. Debugging Block-Based Designs with Signal Tap x
2.10.3.1. Signal Tap Debugging with a Core Partition 2.10.3.2. Signal Tap Debugging with a Root Partition 2.10.3.3. Compiler Snapshots and Signal Tap Debugging
2.10.3.1. Signal Tap Debugging with a Core Partition x
2.10.3.1.1. Partition Boundary Ports Method 2.10.3.1.2. Debug a Core Partition through Partition Boundary Ports 2.10.3.1.3. Export a Core Partition with Partition Boundary Ports 2.10.3.1.4. Signal Tap HDL Instance Method 2.10.3.1.5. Export a Core Partition with Signal Tap HDL Instances 2.10.3.1.6. Debug a Core Partition Exported with Signal Tap HDL Instances
2.10.3.1.4. Signal Tap HDL Instance Method x
2.10.3.1.4.1. Debug a Core Partition Exported with Signal Tap HDL Instances
2.10.3.2. Signal Tap Debugging with a Root Partition x
2.10.3.2.1. Export the Root Partition with SLD JTAG Bridge 2.10.3.2.2. Debugging an Exported Root Partition and Core Partition Simultaneously using the SLD JTAG Bridge
2.10.3.3. Compiler Snapshots and Signal Tap Debugging x
2.10.3.3.1. Add Post-Fit Nodes when Reusing a Partition Containing a Synthesis Snapshot
2.12. Custom State-Based Triggering Flow Examples x
2.12.1. Trigger Example 1: Custom Trigger Position 2.12.2. Trigger Example 2: Trigger When triggercond1 Occurs Ten Times between triggercond2 and triggercond3
2.15. Signal Tap Scripting Support x
2.15.1. Signal Tap Command-Line Options 2.15.2. Data Capture from the Command Line
3. Quick Design Verification with Signal Probe x
3.1. Signal Probe Debugging Flow 3.2. Quick Design Verification with Signal Probe Revision History
3.1. Signal Probe Debugging Flow x
3.1.1. Step 1: Reserve Signal Probe Pins 3.1.2. Step 2: Assign Nodes to Signal Probe Pins 3.1.3. Step 3: Connect the Signal Probe Pin to an Output Pin 3.1.4. Step 4: Compile the Design 3.1.5. (Optional) Step 5: Modify the Signal Probe Pins Assignments 3.1.6. Step 6: Run Fitter-Only Compilation 3.1.7. Step 7: Check Connection Table in Fitter Report
4. In-System Debugging Using External Logic Analyzers x
4.1. About the Quartus® Prime Logic Analyzer Interface 4.2. Choosing a Logic Analyzer 4.3. Flow for Using the LAI 4.4. Controlling the Active Bank During Runtime 4.5. LAI Core Parameters 4.6. In-System Debugging Using External Logic Analyzers Revision History
4.2. Choosing a Logic Analyzer x
4.2.1. Required Components
4.3. Flow for Using the LAI x
4.3.1. Defining Parameters for the Logic Analyzer Interface 4.3.2. Mapping the LAI File Pins to Available I/O Pins 4.3.3. Mapping Internal Signals to the LAI Banks 4.3.4. Compiling Your Quartus® Prime Project 4.3.5. Programming Your Intel-Supported Device Using the LAI
4.4. Controlling the Active Bank During Runtime x
4.4.1. Acquiring Data on Your Logic Analyzer
5. In-System Modification of Memory and Constants x
5.1. IP Cores Supporting In System Memory Content Editor 5.2. Debug Flow with the In-System Memory Content Editor 5.3. Enabling Runtime Modification of Instances in the Design 5.4. Programming the Device with the In-System Memory Content Editor 5.5. Loading Memory Instances to the ISMCE 5.6. Monitoring Locations in Memory 5.7. Editing Memory Contents with the Hex Editor Pane 5.8. Importing and Exporting Memory Files 5.9. Access Two or More Devices 5.10. Scripting Support 5.11. In-System Modification of Memory and Constants Revision History
5.10. Scripting Support x
5.10.1. The insystem_memory_edit Tcl Package
5.10.1. The insystem_memory_edit Tcl Package x
5.10.1.1. Getting Information about the insystem_memory_edit Package
6. Design Debugging Using In-System Sources and Probes x
6.1. Hardware and Software Requirements 6.2. Design Flow Using the In-System Sources and Probes Editor 6.3. Compiling the Design 6.4. Running the In-System Sources and Probes Editor 6.5. Tcl interface for the In-System Sources and Probes Editor 6.6. Design Example: Dynamic PLL Reconfiguration 6.7. Design Debugging Using In-System Sources and Probes Revision History
6.2. Design Flow Using the In-System Sources and Probes Editor x
6.2.1. Instantiating the In-System Sources and Probes IP Core 6.2.2. In-System Sources and Probes IP Core Parameters
6.4. Running the In-System Sources and Probes Editor x
6.4.1. In-System Sources and Probes Editor GUI 6.4.2. Programming Your Device With JTAG Chain Configuration 6.4.3. Instance Manager 6.4.4. In-System Sources and Probes Editor Pane
6.4.4. In-System Sources and Probes Editor Pane x
6.4.4.1. Reading Probe Data 6.4.4.2. Writing Data 6.4.4.3. Organizing Data
7. Analyzing and Debugging Designs with System Console x
7.1. Introduction to System Console 7.2. Starting System Console 7.3. System Console GUI 7.4. Launching a Toolkit in System Console 7.5. Using System Console Services 7.6. On-Board Intel® FPGA Download Cable II Support 7.7. MATLAB* and Simulink* in a System Verification Flow 7.8. System Console Examples and Tutorials 7.9. Running System Console in Command-Line Mode 7.10. Using System Console Commands 7.11. Using Toolkit Tcl Commands 7.12. Analyzing and Debugging Designs with the System Console Revision History
7.1. Introduction to System Console x
7.1.1. IP Cores that Interact with System Console 7.1.2. Services Provided through Debug Agents 7.1.3. System Console Debugging Flow
7.2. Starting System Console x
7.2.1. Customizing System Console Startup
7.3. System Console GUI x
7.3.1. System Console Views 7.3.2. Toolkit Explorer Pane 7.3.3. System Explorer Pane 7.3.4. Customizing, Saving, and Resetting the System Console Layout
7.3.1. System Console Views x
7.3.1.1. Main View 7.3.1.2. Autosweep View 7.3.1.3. Dashboard View 7.3.1.4. Eye Viewer
7.3.1.1. Main View x
7.3.1.1.1. Link Pair View
7.4. Launching a Toolkit in System Console x
7.4.1. Available System Debugging Toolkits 7.4.2. Creating Collections from the Toolkit Explorer 7.4.3. Filtering and Searching Interactive Instances
7.5. Using System Console Services x
7.5.1. Locating Available Services 7.5.2. Opening and Closing Services 7.5.3. Using the SLD Service 7.5.4. Using the In-System Sources and Probes Service 7.5.5. Using the Monitor Service 7.5.6. Using the Device Service 7.5.7. Using the Design Service 7.5.8. Using the Bytestream Service 7.5.9. Using the JTAG Debug Service
7.5.3. Using the SLD Service x
7.5.3.1. SLD Commands
7.5.4. Using the In-System Sources and Probes Service x
7.5.4.1. In-System Sources and Probes Commands
7.5.5. Using the Monitor Service x
7.5.5.1. Monitor Commands
7.5.6. Using the Device Service x
7.5.6.1. Device Commands
7.5.7. Using the Design Service x
7.5.7.1. Design Service Commands
7.5.8. Using the Bytestream Service x
7.5.8.1. Bytestream Commands
7.5.9. Using the JTAG Debug Service x
7.5.9.1. JTAG Debug Commands
7.7. MATLAB* and Simulink* in a System Verification Flow x
7.7.1. Supported MATLAB* API Commands 7.7.2. High Level Flow
7.8. System Console Examples and Tutorials x
7.8.1. Nios® II Processor Example
7.8.1. Nios® II Processor Example x
7.8.1.1. Processor Commands
Answers to Top FAQs
1. System Debugging Tools Overview
2. Design Debugging with the Signal Tap Logic Analyzer
3. Quick Design Verification with Signal Probe
4. In-System Debugging Using External Logic Analyzers
5. In-System Modification of Memory and Constants
6. Design Debugging Using In-System Sources and Probes
7. Analyzing and Debugging Designs with System Console
8. Quartus® Prime Pro Edition User Guide Debug Tools Archives
A. Quartus® Prime Pro Edition User Guides

6.6. Design Example: Dynamic PLL Reconfiguration

The In-System Sources and Probes Editor can help you create a virtual front panel during the prototyping phase of your design. You can create relatively simple, high functioning designs of in a short amount of time. The following PLL reconfiguration example demonstrates how to use the In-System Sources and Probes Editor to provide a GUI to dynamically reconfigure a Stratix® PLL.

Stratix® PLLs allow you to dynamically update PLL coefficients during run time. Each enhanced PLL within the Stratix® device contains a register chain that allows you to modify the pre-scale counters (m and n values), output divide counters, and delay counters. In addition, the ALTPLL_RECONFIG IP core provides an easy interface to access the register chain counters. The ALTPLL_RECONFIG IP core provides a cache that contains all modifiable PLL parameters. After you update all the PLL parameters in the cache, the ALTPLL_RECONFIG IP core drives the PLL register chain to update the PLL with the updated parameters. The figure shows a Stratix® -enhanced PLL with reconfigurable coefficients.

Figure 108.  Stratix® -Enhanced PLL with Reconfigurable Coefficients


The following design example uses an ALTSOURCE_PROBE instance to update the PLL parameters in the ALTPLL_RECONFIG IP core cache. The ALTPLL_RECONFIG IP core connects to an enhanced PLL in a Stratix® FPGA to drive the register chain containing the PLL reconfigurable coefficients. This design example uses a Tcl/Tk script to generate a GUI where you can enter in new m and n values for the enhanced PLL. The Tcl script extracts the m and n values from the GUI, shifts the values out to the ALTSOURCE_PROBE instances to update the values in the ALTPLL_RECONFIG IP core cache, and asserts the reconfiguration signal on the ALTPLL_RECONFIG IP core. The reconfiguration signal on the ALTPLL_RECONFIG IP core starts the register chain transaction to update all PLL reconfigurable coefficients.
Figure 109. Block Diagram of Dynamic PLL Reconfiguration Design Example

This design example was created using a Nios® II Development Kit, Stratix® Edition. The file sourceprobe_DE_dynamic_pll.zip contains all the necessary files for running this design example, including the following:

  • Readme.txt—A text file that describes the files contained in the design example and provides instructions about running the Tk GUI shown in the figure below.
  • Interactive_Reconfig.qar—The archived Quartus® Prime project for this design example.
    Figure 110. Interactive PLL Reconfiguration GUI Created with Tk and In-System Sources and Probes Tcl Package


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