Cyclone V Device Datasheet

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ID 683801
Date 5/23/2023
Public
Document Table of Contents
Document Table of Contents x
Cyclone V Device Datasheet
Cyclone V Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Glossary Document Revision History for Cyclone® V Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications OCT Variation after Power-Up Calibration Pin Capacitance Hot Socketing Internal Weak Pull-Up Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Differential HSTL and HSUL I/O Standards Differential I/O Standard Specifications
Switching Characteristics x
Transceiver Performance Specifications Core Performance Specifications Periphery Performance HPS Specifications
Transceiver Performance Specifications x
Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain Typical TX VOD Setting for Cyclone® V Transceiver Channels with termination of 100 Ω Transmitter Pre-Emphasis Levels Transceiver Compliance Specification
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Performance Specifications Memory Block Performance Specifications
Periphery Performance x
High-Speed I/O Specifications DLL Frequency Range Specifications DQS Logic Block Specifications Memory Output Clock Jitter Specifications OCT Calibration Block Specifications Duty Cycle Distortion (DCD) Specifications
HPS Specifications x
HPS Clock Performance HPS PLL Specifications Quad SPI Flash Timing Characteristics SPI Timing Characteristics SD/MMC Timing Characteristics USB Timing Characteristics Ethernet Media Access Controller (EMAC) Timing Characteristics I2C Timing Characteristics NAND Timing Characteristics Arm* Trace Timing Characteristics UART Interface GPIO Interface CAN Interface HPS JTAG Timing Specifications
HPS PLL Specifications x
HPS PLL VCO Frequency Range HPS PLL Input Clock Range HPS PLL Input Jitter
Configuration Specifications x
POR Specifications FPGA JTAG Configuration Timing FPP Configuration Timing Active Serial (AS) Configuration Timing DCLK Frequency Specification in the AS Configuration Scheme Passive Serial (PS) Configuration Timing Initialization Configuration Files Minimum Configuration Time Estimation Remote System Upgrades User Watchdog Internal Oscillator Frequency Specifications
FPP Configuration Timing x
DCLK-to-DATA[] Ratio (r) for FPP Configuration FPP Configuration Timing when DCLK-to-DATA[] = 1 FPP Configuration Timing when DCLK-to-DATA[] >1
I/O Timing x
Programmable IOE Delay Programmable Output Buffer Delay
Cyclone V Device Datasheet

PLL Specifications

Table 31.  PLL Specifications for Cyclone® V DevicesThis table lists the Cyclone® V PLL block specifications. Cyclone® V PLL block does not include HPS PLL.
Symbol Parameter Condition Min Typ Max Unit
fIN Input clock frequency –C6 speed grade 5 — 670 52 MHz
–C7, –I7 speed grades 5 — 62252 MHz
–C8, –A7 speed grades 5 — 50052 MHz
fINPFD Integer input clock frequency to the phase frequency detector (PFD) — 5 — 325 MHz
fFINPFD Fractional input clock frequency to the PFD — 50 — 160 MHz
fVCO 53 PLL voltage-controlled oscillator (VCO) operating range –C6, –C7, –I7 speed grades 600 — 1600 MHz
–C8, –A7 speed grades 600 — 1300 MHz
tEINDUTY Input clock or external feedback clock input duty cycle — 40 — 60 %
fOUT Output frequency for internal global or regional clock –C6, –C7, –I7 speed grades — — 550 54 MHz
–C8, –A7 speed grades — — 46054 MHz
fOUT_EXT Output frequency for external clock output –C6, –C7, –I7 speed grades — — 66754 MHz
–C8, –A7 speed grades — — 53354 MHz
tOUTDUTY Duty cycle for external clock output (when set to 50%) — 45 50 55 %
tFCOMP External feedback clock compensation time — — — 10 ns
tDYCONFIGCLK Dynamic configuration clock for mgmt_clk and scanclk — — — 100 MHz
tLOCK Time required to lock from end-of-device configuration or deassertion of areset — — — 1 ms
tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) — — — 1 ms
fCLBW PLL closed-loop bandwidth Low — 0.3 — MHz
Medium — 1.5 — MHz
High55 — 4 — MHz
tPLL_PSERR Accuracy of PLL phase shift — — — ±50 ps
tARESET Minimum pulse width on the areset signal — 10 — — ns
tINCCJ 56 57 Input clock cycle-to-cycle jitter FREF ≥ 100 MHz — — 0.15 UI (p-p)
FREF < 100 MHz — — ±750 ps (p-p)
tOUTPJ_DC 58 Period jitter for dedicated clock output in integer PLL FOUT ≥ 100 MHz — — 300 ps (p-p)
FOUT < 100 MHz — — 30 mUI (p-p)
tFOUTPJ_DC 58 Period jitter for dedicated clock output in fractional PLL FOUT ≥ 100 MHz — — 42561, 300 59 ps (p-p)
FOUT < 100 MHz — — 42.561, 3059 mUI (p-p)
tOUTCCJ_DC 58 Cycle-to-cycle jitter for dedicated clock output in integer PLL FOUT ≥ 100 MHz — — 300 ps (p-p)
FOUT < 100 MHz — — 30 mUI (p-p)
tFOUTCCJ_DC 58 Cycle-to-cycle jitter for dedicated clock output in fractional PLL FOUT ≥ 100 MHz — — 42561, 30059 ps (p-p)
FOUT < 100 MHz — — 42.561, 3059 mUI (p-p)
tOUTPJ_IO 58 60 Period jitter for clock output on a regular I/O in integer PLL FOUT ≥ 100 MHz — — 650 ps (p-p)
FOUT < 100 MHz — — 65 mUI (p-p)
tFOUTPJ_IO 58 60 61 Period jitter for clock output on a regular I/O in fractional PLL FOUT ≥ 100 MHz — — 650 ps (p-p)
FOUT < 100 MHz — — 65 mUI (p-p)
tOUTCCJ_IO 58 60 Cycle-to-cycle jitter for clock output on regular I/O in integer PLL FOUT ≥ 100 MHz — — 650 ps (p-p)
FOUT < 100 MHz — — 65 mUI (p-p)
tFOUTCCJ_IO 58 60 61 Cycle-to-cycle jitter for clock output on regular I/O in fractional PLL FOUT ≥ 100 MHz — — 650 ps (p-p)
FOUT < 100 MHz — — 65 mUI (p-p)
tCASC_OUTPJ_DC 58 62 Period jitter for dedicated clock output in cascaded PLLs FOUT ≥ 100 MHz — — 300 ps (p-p)
FOUT < 100 MHz — — 30 mUI (p-p)
tDRIFT Frequency drift after PFDENA is disabled for a duration of 100 µs — — — ±10 %
dKBIT Bit number of Delta Sigma Modulator (DSM) — 8 24 32 Bits
kVALUE Numerator of fraction — 128 8388608 2147483648 —
fRES Resolution of VCO frequency fINPFD = 100 MHz 390625 5.96 0.023 Hz
Related Information
52 This specification is limited in the Intel® Quartus® Prime software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.
53 The VCO frequency reported by the Intel® Quartus® Prime software takes into consideration the VCO post divider value. Therefore, if the VCO post divider value is 2, the frequency reported can be lower than the fVCO specification.
54 This specification is limited by the lower of the two: I/O fMAX or FOUT of the PLL.
55 High bandwidth PLL settings are not supported in external feedback mode.
56 A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps.
57 FREF is fIN/N, specification applies when N = 1.
58 Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a different measurement method and are available in Memory Output Clock Jitter Specification for Cyclone® V Devices table.
59 This specification only covers fractional PLL for low bandwidth. The fVCO for fractional value range 0.20–0.80 must be ≥ 1200 MHz.
60 External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter Specification for Cyclone® V Devices table.
61 This specification only covers fractional PLL for low bandwidth. The fVCO for fractional value range 0.05–0.95 must be ≥ 1000 MHz.
62 The cascaded PLL specification is only applicable with the following conditions:
  • Upstream PLL: 0.59 MHz ≤ Upstream PLL BW < 1 MHz
  • Downstream PLL: Downstream PLL BW > 2 MHz
Level Two Title