Cyclone V Device Datasheet

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ID 683801
Date 5/23/2023
Public
Document Table of Contents
Document Table of Contents x
Cyclone V Device Datasheet
Cyclone V Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Glossary Document Revision History for Cyclone® V Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications OCT Variation after Power-Up Calibration Pin Capacitance Hot Socketing Internal Weak Pull-Up Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Differential HSTL and HSUL I/O Standards Differential I/O Standard Specifications
Switching Characteristics x
Transceiver Performance Specifications Core Performance Specifications Periphery Performance HPS Specifications
Transceiver Performance Specifications x
Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain Typical TX VOD Setting for Cyclone® V Transceiver Channels with termination of 100 Ω Transmitter Pre-Emphasis Levels Transceiver Compliance Specification
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Performance Specifications Memory Block Performance Specifications
Periphery Performance x
High-Speed I/O Specifications DLL Frequency Range Specifications DQS Logic Block Specifications Memory Output Clock Jitter Specifications OCT Calibration Block Specifications Duty Cycle Distortion (DCD) Specifications
HPS Specifications x
HPS Clock Performance HPS PLL Specifications Quad SPI Flash Timing Characteristics SPI Timing Characteristics SD/MMC Timing Characteristics USB Timing Characteristics Ethernet Media Access Controller (EMAC) Timing Characteristics I2C Timing Characteristics NAND Timing Characteristics Arm* Trace Timing Characteristics UART Interface GPIO Interface CAN Interface HPS JTAG Timing Specifications
HPS PLL Specifications x
HPS PLL VCO Frequency Range HPS PLL Input Clock Range HPS PLL Input Jitter
Configuration Specifications x
POR Specifications FPGA JTAG Configuration Timing FPP Configuration Timing Active Serial (AS) Configuration Timing DCLK Frequency Specification in the AS Configuration Scheme Passive Serial (PS) Configuration Timing Initialization Configuration Files Minimum Configuration Time Estimation Remote System Upgrades User Watchdog Internal Oscillator Frequency Specifications
FPP Configuration Timing x
DCLK-to-DATA[] Ratio (r) for FPP Configuration FPP Configuration Timing when DCLK-to-DATA[] = 1 FPP Configuration Timing when DCLK-to-DATA[] >1
I/O Timing x
Programmable IOE Delay Programmable Output Buffer Delay
Cyclone V Device Datasheet

Glossary

Table 71.  Glossary
Term Definition
Differential I/O standards

Receiver Input Waveforms



Transmitter Output Waveforms



fHSCLK Left/right PLL input clock frequency.
fHSDR High-speed I/O block—Maximum/minimum LVDS data transfer rate (fHSDR =1/TUI).
J High-speed I/O block—Deserialization factor (width of parallel data bus).
JTAG timing specifications

JTAG Timing Specifications



PLL specifications

Diagram of PLL specifications



RL Receiver differential input discrete resistor (external to the Cyclone® V device).
Sampling window (SW)

Timing diagram—The period of time during which the data must be valid in order to capture it correctly. The setup and hold times determine the ideal strobe position in the sampling window, as shown:



Single-ended voltage referenced I/O standard

The JEDEC standard for the SSTL and HSTL I/O defines both the AC and DC input signal values. The AC values indicate the voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. After the receiver input has crossed the AC value, the receiver changes to the new logic state.

The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform ringing.

Single-Ended Voltage Referenced I/O Standard
tC High-speed receiver/transmitter input and output clock period.
TCCS (channel-to-channel-skew) The timing difference between the fastest and slowest output edges, including the tCO variation and clock skew, across channels driven by the same PLL. The clock is included in the TCCS measurement (refer to the Timing Diagram figure under SW in this table).
tDUTY High-speed I/O block—Duty cycle on high-speed transmitter output clock.
tFALL Signal high-to-low transition time (80–20%)
tINCCJ Cycle-to-cycle jitter tolerance on the PLL clock input
tOUTPJ_IO Period jitter on the GPIO driven by a PLL
tOUTPJ_DC Period jitter on the dedicated clock output driven by a PLL
tRISE Signal low-to-high transition time (20–80%)
Timing Unit Interval (TUI) The timing budget allowed for skew, propagation delays, and the data sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w)
VCM(DC) DC common mode input voltage.
VICM Input common mode voltage—The common mode of the differential signal at the receiver.
VID Input differential voltage swing—The difference in voltage between the positive and complementary conductors of a differential transmission at the receiver.
VDIF(AC) AC differential input voltage—Minimum AC input differential voltage required for switching.
VDIF(DC) DC differential input voltage— Minimum DC input differential voltage required for switching.
VIH Voltage input high—The minimum positive voltage applied to the input which is accepted by the device as a logic high.
VIH(AC) High-level AC input voltage
VIH(DC) High-level DC input voltage
VIL Voltage input low—The maximum positive voltage applied to the input which is accepted by the device as a logic low.
VIL(AC) Low-level AC input voltage
VIL(DC) Low-level DC input voltage
VOCM Output common mode voltage—The common mode of the differential signal at the transmitter.
VOD Output differential voltage swing—The difference in voltage between the positive and complementary conductors of a differential transmission line at the transmitter.
VSWING Differential input voltage
VX Input differential cross point voltage
VOX Output differential cross point voltage
W High-speed I/O block—Clock boost factor
Level Two Title