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Ixiasoft
Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices
CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain
CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain
Typical TX VOD Setting for Cyclone® V Transceiver Channels with termination of 100 Ω
Transmitter Pre-Emphasis Levels
Transceiver Compliance Specification
HPS Clock Performance
HPS PLL Specifications
Quad SPI Flash Timing Characteristics
SPI Timing Characteristics
SD/MMC Timing Characteristics
USB Timing Characteristics
Ethernet Media Access Controller (EMAC) Timing Characteristics
I2C Timing Characteristics
NAND Timing Characteristics
Arm* Trace Timing Characteristics
UART Interface
GPIO Interface
CAN Interface
HPS JTAG Timing Specifications
POR Specifications
FPGA JTAG Configuration Timing
FPP Configuration Timing
Active Serial (AS) Configuration Timing
DCLK Frequency Specification in the AS Configuration Scheme
Passive Serial (PS) Configuration Timing
Initialization
Configuration Files
Minimum Configuration Time Estimation
Remote System Upgrades
User Watchdog Internal Oscillator Frequency Specifications
Visible to Intel only — GUID: mcn1419933398989
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I/O Standard Specifications
Tables in this section list the input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH and IOL) for various I/O standards supported by Cyclone® V devices.
You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.