Cyclone V Device Datasheet

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ID 683801
Date 5/23/2023
Public
Document Table of Contents
Document Table of Contents x
Cyclone V Device Datasheet
Cyclone V Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Glossary Document Revision History for Cyclone® V Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications OCT Variation after Power-Up Calibration Pin Capacitance Hot Socketing Internal Weak Pull-Up Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Differential HSTL and HSUL I/O Standards Differential I/O Standard Specifications
Switching Characteristics x
Transceiver Performance Specifications Core Performance Specifications Periphery Performance HPS Specifications
Transceiver Performance Specifications x
Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain Typical TX VOD Setting for Cyclone® V Transceiver Channels with termination of 100 Ω Transmitter Pre-Emphasis Levels Transceiver Compliance Specification
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Performance Specifications Memory Block Performance Specifications
Periphery Performance x
High-Speed I/O Specifications DLL Frequency Range Specifications DQS Logic Block Specifications Memory Output Clock Jitter Specifications OCT Calibration Block Specifications Duty Cycle Distortion (DCD) Specifications
HPS Specifications x
HPS Clock Performance HPS PLL Specifications Quad SPI Flash Timing Characteristics SPI Timing Characteristics SD/MMC Timing Characteristics USB Timing Characteristics Ethernet Media Access Controller (EMAC) Timing Characteristics I2C Timing Characteristics NAND Timing Characteristics Arm* Trace Timing Characteristics UART Interface GPIO Interface CAN Interface HPS JTAG Timing Specifications
HPS PLL Specifications x
HPS PLL VCO Frequency Range HPS PLL Input Clock Range HPS PLL Input Jitter
Configuration Specifications x
POR Specifications FPGA JTAG Configuration Timing FPP Configuration Timing Active Serial (AS) Configuration Timing DCLK Frequency Specification in the AS Configuration Scheme Passive Serial (PS) Configuration Timing Initialization Configuration Files Minimum Configuration Time Estimation Remote System Upgrades User Watchdog Internal Oscillator Frequency Specifications
FPP Configuration Timing x
DCLK-to-DATA[] Ratio (r) for FPP Configuration FPP Configuration Timing when DCLK-to-DATA[] = 1 FPP Configuration Timing when DCLK-to-DATA[] >1
I/O Timing x
Programmable IOE Delay Programmable Output Buffer Delay
Cyclone V Device Datasheet

Absolute Maximum Ratings

This section defines the maximum operating conditions for Cyclone® V devices. The values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms.

The functional operation of the device is not implied for these conditions.

CAUTION:
Conditions outside the range listed in the following table may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device.
Table 2.  Absolute Maximum Ratings for Cyclone® V Devices
Symbol Description Minimum Maximum Unit
VCC Core voltage and periphery circuitry power supply –0.5 1.43 V
VCCPGM Configuration pins power supply –0.5 3.90 V
VCC_AUX Auxiliary supply –0.5 3.25 V
VCCBAT Battery back-up power supply for design security volatile key register –0.5 3.90 V
VCCPD I/O pre-driver power supply –0.5 3.90 V
VCCIO I/O power supply –0.5 3.90 V
VCCA_FPLL Phase-locked loop (PLL) analog power supply –0.5 3.25 V
VCCH_GXB Transceiver high voltage power –0.5 3.25 V
VCCE_GXB Transceiver power –0.5 1.50 V
VCCL_GXB Transceiver clock network power –0.5 1.50 V
VI DC input voltage –0.5 3.80 V
VCC_HPS HPS core voltage and periphery circuitry power supply –0.5 1.43 V
VCCPD_HPS HPS I/O pre-driver power supply –0.5 3.90 V
VCCIO_HPS HPS I/O power supply –0.5 3.90 V
VCCRSTCLK_HPS HPS reset and clock input pins power supply –0.5 3.90 V
VCCPLL_HPS HPS PLL analog power supply –0.5 3.25 V
VCC_AUX_SHARED 1 HPS auxiliary power supply –0.5 3.25 V
IOUT DC output current per pin –25 40 mA
TJ Operating junction temperature –55 125 °C
TSTG Storage temperature (no bias) –65 150 °C
1 VCC_AUX_SHARED must be powered by the same source as VCC_AUX for Cyclone® V SX C5, C6, D5, and D6 devices, and Cyclone® V SE A5 and A6 devices.
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