Cyclone V Device Datasheet

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ID 683801
Date 5/23/2023
Public
Document Table of Contents
Document Table of Contents x
Cyclone V Device Datasheet
Cyclone V Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Glossary Document Revision History for Cyclone® V Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications OCT Variation after Power-Up Calibration Pin Capacitance Hot Socketing Internal Weak Pull-Up Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Differential HSTL and HSUL I/O Standards Differential I/O Standard Specifications
Switching Characteristics x
Transceiver Performance Specifications Core Performance Specifications Periphery Performance HPS Specifications
Transceiver Performance Specifications x
Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain Typical TX VOD Setting for Cyclone® V Transceiver Channels with termination of 100 Ω Transmitter Pre-Emphasis Levels Transceiver Compliance Specification
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Performance Specifications Memory Block Performance Specifications
Periphery Performance x
High-Speed I/O Specifications DLL Frequency Range Specifications DQS Logic Block Specifications Memory Output Clock Jitter Specifications OCT Calibration Block Specifications Duty Cycle Distortion (DCD) Specifications
HPS Specifications x
HPS Clock Performance HPS PLL Specifications Quad SPI Flash Timing Characteristics SPI Timing Characteristics SD/MMC Timing Characteristics USB Timing Characteristics Ethernet Media Access Controller (EMAC) Timing Characteristics I2C Timing Characteristics NAND Timing Characteristics Arm* Trace Timing Characteristics UART Interface GPIO Interface CAN Interface HPS JTAG Timing Specifications
HPS PLL Specifications x
HPS PLL VCO Frequency Range HPS PLL Input Clock Range HPS PLL Input Jitter
Configuration Specifications x
POR Specifications FPGA JTAG Configuration Timing FPP Configuration Timing Active Serial (AS) Configuration Timing DCLK Frequency Specification in the AS Configuration Scheme Passive Serial (PS) Configuration Timing Initialization Configuration Files Minimum Configuration Time Estimation Remote System Upgrades User Watchdog Internal Oscillator Frequency Specifications
FPP Configuration Timing x
DCLK-to-DATA[] Ratio (r) for FPP Configuration FPP Configuration Timing when DCLK-to-DATA[] = 1 FPP Configuration Timing when DCLK-to-DATA[] >1
I/O Timing x
Programmable IOE Delay Programmable Output Buffer Delay
Cyclone V Device Datasheet

Memory Output Clock Jitter Specifications

Table 37.  Memory Output Clock Jitter Specifications for Cyclone® V Devices

The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard.

The memory output clock jitter is applicable when an input jitter of 30 ps (p-p) is applied with bit error rate (BER) 10–12, equivalent to 14 sigma.

Intel recommends using the UniPHY intellectual property (IP) with PHYCLK connections for better jitter performance.

Parameter Clock Network Symbol –C6 –C7, –I7 –C8 Unit
Min Max Min Max Min Max
Clock period jitter PHYCLK tJIT(per) –60 60 –70 70 –70 70 ps
Cycle-to-cycle period jitter PHYCLK tJIT(cc) — 90 — 100 — 100 ps
Level Two Title