Visible to Intel only — GUID: sam1394083334363
Ixiasoft
1. Intel® MAX® 10 I/O Overview
2. Intel® MAX® 10 I/O Architecture and Features
3. Intel® MAX® 10 I/O Design Considerations
4. Intel® MAX® 10 I/O Implementation Guides
5. GPIO Lite Intel® FPGA IP References
6. Intel® MAX® 10 General Purpose I/O User Guide Archives
7. Document Revision History for Intel® MAX® 10 General Purpose I/O User Guide
2.3.2.1. Programmable Open Drain
2.3.2.2. Programmable Bus Hold
2.3.2.3. Programmable Pull-Up Resistor
2.3.2.4. Programmable Current Strength
2.3.2.5. Programmable Output Slew Rate Control
2.3.2.6. Programmable IOE Delay
2.3.2.7. PCI Clamp Diode
2.3.2.8. Programmable Pre-Emphasis
2.3.2.9. Programmable Differential Output Voltage
2.3.2.10. Programmable Emulated Differential Output
2.3.2.11. Programmable Dynamic Power Down
3.1. Guidelines: VCCIO Range Considerations
3.2. Guidelines: Voltage-Referenced I/O Standards Restriction
3.3. Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers
3.4. Guidelines: Adhere to the LVDS I/O Restrictions Rules
3.5. Guidelines: I/O Restriction Rules
3.6. Guidelines: Placement Restrictions for 1.0 V I/O Pin
3.7. Guidelines: Analog-to-Digital Converter I/O Restriction
3.8. Guidelines: External Memory Interface I/O Restrictions
3.9. Guidelines: Dual-Purpose Configuration Pin
3.10. Guidelines: Clock and Data Input Signal for Intel® MAX® 10 E144 Package
Visible to Intel only — GUID: sam1394083334363
Ixiasoft
2.3.2.7. PCI Clamp Diode
The Intel® MAX® 10 devices are equipped with optional PCI clamp diode that you can enable for the input and output of each I/O pin. You can use this diode to protect I/O pins during voltage overshoot.
The PCI clamp diode is available in the Intel® Quartus® Prime software for the following I/O standards:
- 3.3 V LVTTL/3.3 V LVCMOS
- 3.0 V LVTTL/3.0 V LVCMOS
- 2.5 V LVTTL/2.5 V LVCMOS
- 3.0 V PCI
- 3.3 V Schmitt Trigger
- 2.5 V Schmitt Trigger
Dual-purpose configuration pins support the diode in user mode if you do not use the pins as configuration pins for the selected configuration scheme. The dedicated configuration pins do not support the on-chip diode.