Visible to Intel only — GUID: sam1398702830416
Ixiasoft
1. Intel® MAX® 10 I/O Overview
2. Intel® MAX® 10 I/O Architecture and Features
3. Intel® MAX® 10 I/O Design Considerations
4. Intel® MAX® 10 I/O Implementation Guides
5. GPIO Lite Intel® FPGA IP References
6. Intel® MAX® 10 General Purpose I/O User Guide Archives
7. Document Revision History for Intel® MAX® 10 General Purpose I/O User Guide
2.3.2.1. Programmable Open Drain
2.3.2.2. Programmable Bus Hold
2.3.2.3. Programmable Pull-Up Resistor
2.3.2.4. Programmable Current Strength
2.3.2.5. Programmable Output Slew Rate Control
2.3.2.6. Programmable IOE Delay
2.3.2.7. PCI Clamp Diode
2.3.2.8. Programmable Pre-Emphasis
2.3.2.9. Programmable Differential Output Voltage
2.3.2.10. Programmable Emulated Differential Output
2.3.2.11. Programmable Dynamic Power Down
3.1. Guidelines: VCCIO Range Considerations
3.2. Guidelines: Voltage-Referenced I/O Standards Restriction
3.3. Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers
3.4. Guidelines: Adhere to the LVDS I/O Restrictions Rules
3.5. Guidelines: I/O Restriction Rules
3.6. Guidelines: Placement Restrictions for 1.0 V I/O Pin
3.7. Guidelines: Analog-to-Digital Converter I/O Restriction
3.8. Guidelines: External Memory Interface I/O Restrictions
3.9. Guidelines: Dual-Purpose Configuration Pin
3.10. Guidelines: Clock and Data Input Signal for Intel® MAX® 10 E144 Package
Visible to Intel only — GUID: sam1398702830416
Ixiasoft
4.1.1. GPIO Lite Intel® FPGA IP Data Paths
Data Path | Mode | ||
---|---|---|---|
Bypass | Single Register | DDR | |
Input | Data goes from the delay element to the core, bypassing all double data rate I/Os (DDIOs). | The full-rate DDIO operates as a single register. | The full-rate DDIO operates as a regular DDIO. |
Output | Data goes from the core straight to the delay element, bypassing all DDIOs. | The full-rate DDIO operates as a single register. | The full-rate DDIO operates as a regular DDIO. |
Bidirectional | The output buffer drives both an output pin and an input buffer. | The full-rate DDIO operates as a single register. The output buffer drives both an output pin and an input buffer. | The full-rate DDIO operates as a regular DDIO. The output buffer drives both an output pin and an input buffer. The input buffer drives a set of three flip-flops. |
If you use asynchronous clear and preset signals, all DDIOs share these same signals.