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1. Intel® MAX® 10 I/O Overview
2. Intel® MAX® 10 I/O Architecture and Features
3. Intel® MAX® 10 I/O Design Considerations
4. Intel® MAX® 10 I/O Implementation Guides
5. GPIO Lite Intel® FPGA IP References
6. Intel® MAX® 10 General Purpose I/O User Guide Archives
7. Document Revision History for Intel® MAX® 10 General Purpose I/O User Guide
2.3.2.1. Programmable Open Drain
2.3.2.2. Programmable Bus Hold
2.3.2.3. Programmable Pull-Up Resistor
2.3.2.4. Programmable Current Strength
2.3.2.5. Programmable Output Slew Rate Control
2.3.2.6. Programmable IOE Delay
2.3.2.7. PCI Clamp Diode
2.3.2.8. Programmable Pre-Emphasis
2.3.2.9. Programmable Differential Output Voltage
2.3.2.10. Programmable Emulated Differential Output
2.3.2.11. Programmable Dynamic Power Down
3.1. Guidelines: VCCIO Range Considerations
3.2. Guidelines: Voltage-Referenced I/O Standards Restriction
3.3. Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers
3.4. Guidelines: Adhere to the LVDS I/O Restrictions Rules
3.5. Guidelines: I/O Restriction Rules
3.6. Guidelines: Placement Restrictions for 1.0 V I/O Pin
3.7. Guidelines: Analog-to-Digital Converter I/O Restriction
3.8. Guidelines: External Memory Interface I/O Restrictions
3.9. Guidelines: Dual-Purpose Configuration Pin
3.10. Guidelines: Clock and Data Input Signal for Intel® MAX® 10 E144 Package
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3.6.1. Calculating the Total Inductance for 1.0 V Pin Placement
You can calculate the total inductance of the surrounding pins by using mutual inductance values in the max10-1v-mutual-coupling.zip file.
- Download the max10-1v-mutual-coupling.zip file and extract the relevant mutual inductance spreadsheet for your device.
- In the mutual inductance spreadsheet, identify the pins in use.
- Calculate the total mutual inductance of the pin and surrounding pins in use to ensure that the placement adheres to the 1.0 V pin placement guideline.
- If the total inductance is above the guideline restriction, update your design to use other I/O pins that contribute less mutual inductance.
Total Mutual Inductance Calculation
Example Condition | Type | Example Result |
---|---|---|
Pin F5 is assigned with the 1 V I/O standard. The surrounding pins, F4, H3, and H4 are in the same I/O bank and are also assigned with the 1.0 V I/O standard. | Intrabank, all 1.0 V | Total Lm of F4, H3, and H4 does not exceed 7.4 nH. The placement does not violate the restriction. |
Pin F5 is assigned with the 1 V I/O standard. The surrounding pins, F4, H3, and H4 are in an adjacent I/O bank and are assigned with the 1.0 V I/O standard. | Interbank, all 1.0 V | Total Lm of F4, H3, and H4 does not exceed 7.4 nH. The placement does not violate the restriction. |
Pin F5 is assigned with the 1 V I/O standard. The surrounding pins, F4, H3, and H4 are in an adjacent I/O bank and are assigned with the 2.5 V I/O standard. | Interbank, mixed voltages | Total Lm of F4, H3, and H4 exceeds 1.0 nH. Update your design to use other I/O pins with smaller mutual inductance. |
Pin Name | Mutual Coupling Pin | Mutual Inductance (nH) |
---|---|---|
F5 | F5 | 3.496 13 |
F5 | F4 | 1.378 |
F5 | H3 | 0.273 |
F5 | J4 | 0.263 |
F5 | K4 | 0.222 |
F5 | E4 | 0.194 |
F5 | F3 | 0.176 |
F5 | H4 | 0.175 |
F5 | E3 | 0.174 |
F5 | G3 | 0.167 |
F5 | G4 | 0.161 |
13 Self inductance for pin F5. Omit this value from the Lm calculation.