Visible to Intel only — GUID: sam1394015065219
Ixiasoft
Visible to Intel only — GUID: sam1394015065219
Ixiasoft
2.2. Intel® MAX® 10 I/O Elements
The Intel® MAX® 10 I/O elements (IOEs) contain a bidirectional I/O buffer and five registers for registering input, output, output-enable signals, and complete embedded bidirectional single data rate (SDR) and double data rate (DDR) transfer.
The I/O buffers are grouped into groups of four I/O modules per I/O bank:
- The Intel® MAX® 10 devices share the user I/O pins with the VREF, RUP, RDN, CLKPIN, PLLCLKOUT, configuration, and test pins.
- Schmitt Trigger input buffer is available in all I/O buffers.
- When the Intel® MAX® 10 device is blank or erased, the I/Os are tri-stated.
Each IOE contains one input register, two output registers, and two output-enable (OE) registers:
- The two output registers and two OE registers are used for DDR applications.
- You can use the input registers for fast setup times and output registers for fast clock-to-output times.
- You can use the OE registers for fast clock-to-output enable times.
You can use the IOEs for input, output, or bidirectional data paths. The I/O pins support various single-ended and differential I/O standards.