Intel® MAX® 10 General Purpose I/O User Guide

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ID 683751
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 I/O Overview 2. Intel® MAX® 10 I/O Architecture and Features 3. Intel® MAX® 10 I/O Design Considerations 4. Intel® MAX® 10 I/O Implementation Guides 5. GPIO Lite Intel® FPGA IP References 6. Intel® MAX® 10 General Purpose I/O User Guide Archives 7. Document Revision History for Intel® MAX® 10 General Purpose I/O User Guide
1. Intel® MAX® 10 I/O Overview x
1.1. Intel® MAX® 10 Devices I/O Resources Per Package 1.2. Intel® MAX® 10 I/O Vertical Migration Support
2. Intel® MAX® 10 I/O Architecture and Features x
2.1. Intel® MAX® 10 I/O Standards Support 2.2. Intel® MAX® 10 I/O Elements 2.3. Intel® MAX® 10 I/O Buffers 2.4. I/O Standards Termination
2.1. Intel® MAX® 10 I/O Standards Support x
2.1.1. Intel® MAX® 10 I/O Standards Voltage and Pin Support
2.2. Intel® MAX® 10 I/O Elements x
2.2.1. Intel® MAX® 10 I/O Banks Architecture 2.2.2. Intel® MAX® 10 I/O Banks Performance 2.2.3. Intel® MAX® 10 I/O Banks Locations
2.3. Intel® MAX® 10 I/O Buffers x
2.3.1. Schmitt-Trigger Input Buffer 2.3.2. Programmable I/O Buffer Features
2.3.2. Programmable I/O Buffer Features x
2.3.2.1. Programmable Open Drain 2.3.2.2. Programmable Bus Hold 2.3.2.3. Programmable Pull-Up Resistor 2.3.2.4. Programmable Current Strength 2.3.2.5. Programmable Output Slew Rate Control 2.3.2.6. Programmable IOE Delay 2.3.2.7. PCI Clamp Diode 2.3.2.8. Programmable Pre-Emphasis 2.3.2.9. Programmable Differential Output Voltage 2.3.2.10. Programmable Emulated Differential Output 2.3.2.11. Programmable Dynamic Power Down
2.4. I/O Standards Termination x
2.4.1. Voltage-Referenced I/O Standards Termination 2.4.2. Differential I/O Standards Termination 2.4.3. Intel® MAX® 10 On-Chip I/O Termination
2.4.3. Intel® MAX® 10 On-Chip I/O Termination x
2.4.3.1. OCT Calibration 2.4.3.2. RS OCT in Intel® MAX® 10 Devices
3. Intel® MAX® 10 I/O Design Considerations x
3.1. Guidelines: VCCIO Range Considerations 3.2. Guidelines: Voltage-Referenced I/O Standards Restriction 3.3. Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers 3.4. Guidelines: Adhere to the LVDS I/O Restrictions Rules 3.5. Guidelines: I/O Restriction Rules 3.6. Guidelines: Placement Restrictions for 1.0 V I/O Pin 3.7. Guidelines: Analog-to-Digital Converter I/O Restriction 3.8. Guidelines: External Memory Interface I/O Restrictions 3.9. Guidelines: Dual-Purpose Configuration Pin 3.10. Guidelines: Clock and Data Input Signal for Intel® MAX® 10 E144 Package
3.6. Guidelines: Placement Restrictions for 1.0 V I/O Pin x
3.6.1. Calculating the Total Inductance for 1.0 V Pin Placement
4. Intel® MAX® 10 I/O Implementation Guides x
4.1. GPIO Lite Intel FPGA IP GPIO Lite Intel® FPGA IP 4.2. Verifying Pin Migration Compatibility
4.1. GPIO Lite Intel FPGA IP GPIO Lite Intel® FPGA IP x
4.1.1. GPIO Lite Intel® FPGA IP Data Paths
4.1.1. GPIO Lite Intel® FPGA IP Data Paths x
4.1.1.1. DDR Input Path 4.1.1.2. DDR Output Path with Output Enable
5. GPIO Lite Intel® FPGA IP References x
5.1. GPIO Lite Intel® FPGA IP Parameter Settings 5.2. GPIO Lite Intel® FPGA IP Interface Signals
1. Intel® MAX® 10 I/O Overview
2. Intel® MAX® 10 I/O Architecture and Features
3. Intel® MAX® 10 I/O Design Considerations
4. Intel® MAX® 10 I/O Implementation Guides
5. GPIO Lite Intel® FPGA IP References
6. Intel® MAX® 10 General Purpose I/O User Guide Archives
7. Document Revision History for Intel® MAX® 10 General Purpose I/O User Guide

2.3.2. Programmable I/O Buffer Features

The Intel® MAX® 10 I/O buffers support a range of programmable features. These features increase the flexibility of I/O utilization and provide an alternative to reduce the usage of external discrete components such as a pull-up resistor and a diode.
Table 6.  Summary of Supported Intel® MAX® 10 Programmable I/O Buffer Features and Settings
Feature

Setting

Condition Assignment Name Supported I/O Standards
Open Drain On, Off (default) To enable this feature, use the OPNDRN primitive. —
  • 3.0 V and 3.3 V LVTTL
  • 1.0 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V, and 3.3 V LVCMOS
  • SSTL-2, SSTL-18, SSTL-15, and SSTL-135
  • 1.2 V, 1.5 V, and 1.8 V HSTL
  • HSUL-12
  • 3.0 V PCI
Bus-Hold On, Off (default) Disabled if you use the weak pull-up resistor feature. Enable Bus-Hold Circuitry
  • 3.0 V and 3.3 V LVTTL
  • 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V, and 3.3 V LVCMOS
  • SSTL-2, SSTL-18, SSTL-15, and SSTL-135
  • 1.2 V, 1.5 V, and 1.8 V HSTL
  • HSUL-12
  • 3.0 V PCI
Pull-up Resistor On, Off (default) Disabled if you use the bus-hold feature. Weak Pull-Up Resistor
Slew Rate Control 0 (Slow), 1 (Medium), 2 (Fast). Default is 2. Disabled if you use OCT. Slew Rate
  • 3.0 V LVTTL
  • 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.0 V LVCMOS
  • SSTL-2, SSTL-18, and SSTL-15
  • 1.2 V, 1.5 V, and 1.8 V HSTL
  • Differential SSTL-2, Differential SSTL-18, and Differential SSTL-15
  • Differential 1.2 V, 1.5 V, and 1.8 V HSTL
PCI Clamp Diode On (default for input pins),

Off (default for output pins, except 3.0 V PCI)

— PCI I/O
  • 3.0 V and 3.3 V LVTTL
  • 2.5 V, 3.0 V, and 3.3 V LVCMOS
  • 3.0 V PCI
  • 2.5 V, 3.0 V, and 3.3 V Schmitt Trigger
Pre-Emphasis 0 (disabled), 1 (enabled). Default is 1. — Programmable Pre-emphasis
  • LVDS
  • RSDS
  • PPDS
  • Mini-LVDS
Differential Output Voltage 0 (low), 1 (medium), 2 (high). Default is 2. — Programmable Differential Output Voltage (VOD)

Section Content
Programmable Open Drain
Programmable Bus Hold
Programmable Pull-Up Resistor
Programmable Current Strength
Programmable Output Slew Rate Control
Programmable IOE Delay
PCI Clamp Diode
Programmable Pre-Emphasis
Programmable Differential Output Voltage
Programmable Emulated Differential Output
Programmable Dynamic Power Down

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