Visible to Intel only — GUID: sam1394084819285
Ixiasoft
Visible to Intel only — GUID: sam1394084819285
Ixiasoft
5.2. GPIO Lite Intel® FPGA IP Interface Signals
Signal Name | Direction | Description |
---|---|---|
pad_in | Input | Input pad port if you use the input path. |
pad_in_b | Input | Input negative pad port if you use the input path and enable the true or pseudo differential buffers. |
pad_out | Output | Output pad port if you use the output path. |
pad_out_b | Output | Output negative pad port if you use the output path and enable the true of pseudo differential buffers. |
pad_io | Bidirectional | Bidirectional pad port if you use bidirectional paths. |
pad_io_b | Bidirectional | Bidirectional negative pad port if you use bidirectional paths and enable true or pseudo differential buffers. |
Signal Name | Direction | Description |
---|---|---|
din | Input | Data received from the input pin. Signal width for each input pin:
|
dout | Output | Data to send out through the output pin. Signal width for each output pin:
|
oe | Input | Control signal that enables the output buffer. This signal is active HIGH. |
nsleep | Input | Control signal that enables the input buffer. This signal is active LOW. This signal is available for the 10M16, 10M25, 10M40, and 10M50 devices. |
Signal Name | Direction | Description |
---|---|---|
inclock | Input | Input clock that clocks the registers in the input path. |
inclocken | Input | Control signal that controls when data is clocked in. This signal is active HIGH. |
outclock | Input | Input clock that clocks the registers in the output path. |
ouctlocken | Input | Control signal that controls when data is clocked out. This signal is active HIGH. |
Signal Name | Direction | Description |
---|---|---|
aclr | Input | Control signal for asynchronous clear that sets the register output state to 0. This signal is active HIGH. |
aset | Input | Control signal for asynchronous preset that sets the register output state to 1. This signal is active HIGH. |
sclr | Input | Control signal for synchronous clear that sets the register output to 0. This signal is active HIGH. |