Intel® MAX® 10 General Purpose I/O User Guide

ID 683751
Date 10/31/2022
Public
Document Table of Contents

3.6. Guidelines: Placement Restrictions for 1.0 V I/O Pin

To minimize the impact of simultaneous switching noise (SSN) on the I/O pins, ensure that the total mutual inductance (Lm) of the I/O pins in usage surrounding the 1.0 V I/O does not exceed the guidelines in the following table.
Table 16.  Total Lm Guidelines for Pins Surrounding the 1.0 V Pin
I/O Standard of Surrounding Pins Locations Relative to 1.0 V Pin Total Lm of Surrounding Pins
1.0 V Within the same bank The total Lm of the surrounding pins in the bank must not exceed 7.41 nH.
In an adjacent bank The total Lm of the surrounding pins in the adjacent bank must not exceed 7.41 nH.
Within the same bank and in an adjacent bank The sum of the total Lm of the surrounding pins in both banks must not exceed 7.41 nH.
Other than 1.0 V In an adjacent bank The total Lm of the surrounding pins in the adjacent bank must not exceed 1 nH.

Example scenarios where the 1.0 V pin is in bank 3 and surrounding pins are in banks 3 and 4:

  • Bank 3 and 4 are both 1.0 V—total Lm of all surrounding pins in both banks must not exceed 7.41 nH.
  • Bank 3 is 1.0 V but bank 4 is 2.5 V—total Lm of surrounding pins in bank 3 must not exceed 7.41 nH and total Lm in bank 4 must not exceed 1 nH.