Low Latency E-Tile 40G Ethernet Intel® FPGA IP Design Example User Guide

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ID 683747
Date 7/12/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description A. Low Latency E-Tile 40G Ethernet Intel FPGA IP Archives 3. Document Revision History for Low Latency E-Tile 40G Ethernet Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design Example 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Changing Target Device in Hardware Design Example 1.6. Testing the Low Latency E-Tile 40G Ethernet Intel® FPGA IP Design in Hardware
1.1. Generating the Design Example x
1.1.1. Design Example Parameters
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Low Latency E-Tile 40G Ethernet Design Example Registers 2.7. Design Example Interface Signals
2.5. Hardware Testing x
2.5.1. Internal Loopback Test 2.5.2. External Loopback Test
1. Quick Start Guide
2. Design Example Description
A. Low Latency E-Tile 40G Ethernet Intel FPGA IP Archives
3. Document Revision History for Low Latency E-Tile 40G Ethernet Design Example User Guide

1.1. Generating the Design Example

Figure 2. Procedure
Figure 3. Example Design Tab in the Low Latency E-Tile 40G Ethernet Parameter EditorSelect Stratix 10 TX E-Tile Transceiver Signal Integrity Development Kit to generate design example for Stratix® 10 devices. Select Intel Agilex 7 F-series Transceiver-SoC Development Kit to generate design example for Intel Agilex® 7 devices.

Follow these steps to generate the hardware design example and testbench:

  1. In the Quartus® Prime Pro Edition software, click File > New Project Wizard to create a new Quartus® Prime project, or File > Open Project to open an existing Quartus® Prime software project. The wizard prompts you to specify a device family and device.
    Note: The design example overwrites the selection with the device on the target board. You specify the target board from the menu of design example options in the Example Design tab (Step 8).

  2. In the IP Catalog, locate and select Low Latency E-Tile 40G Ethernet Intel® FPGA IP . The New IP Variation window appears.
  3. Specify a top-level name for your custom IP variation. The Quartus® Prime IP parameter editor saves the IP variation settings in a file named <your_ip> .ip.
  4. Click OK. The IP parameter editor appears.
  5. On the IP tab, specify the parameters for your IP core variation.
    Note: The Low Latency E-Tile 40G Ethernet Intel® FPGA IP design example does not simulate correctly and does not function correctly if you specify any of the following parameters:
    • Enable preamble pass-through turned on
    • Ready latency set to the value of 3
    • Enable TX CRC insertion turned off
  6. On the Example Design tab, under Example Design Files, enable the Simulation option to generate the testbench, and select the Synthesis option to generate the compilation-only and hardware design examples.
    Note: On the Example Design tab, under Generated HDL Format, only Verilog HDL is available. This IP core does not support VHDL.
  7. Under Target Development Kit select the Stratix 10 TX E-Tile Transceiver Signal Integrity Development Kit or the Intel Agilex 7 F-series Transceiver-SoC Development Kit .
    Note:

    The development kit that you select overwrites the device selection in Step 1.

    • Stratix® 10 E-tile target device is 1SG280LU3F50E3VGS1.
    • Intel Agilex® 7 E-tile device target is AGFB014R24A2E2VR0.
  8. Click the Generate Example Design button. The Select Example Design Directory window appears.
  9. If you want to modify the design example directory path or name from the defaults displayed ( alt_e40c3_0_example_design ), browse to the new path and type the new design example directory name (<design_example_dir>).
  10. Click OK.

Section Content
Design Example Parameters

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