Low Latency E-Tile 40G Ethernet Intel® FPGA IP Design Example User Guide

Download PDF
ID 683747
Date 7/12/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description A. Low Latency E-Tile 40G Ethernet Intel FPGA IP Archives 3. Document Revision History for Low Latency E-Tile 40G Ethernet Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design Example 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Changing Target Device in Hardware Design Example 1.6. Testing the Low Latency E-Tile 40G Ethernet Intel® FPGA IP Design in Hardware
1.1. Generating the Design Example x
1.1.1. Design Example Parameters
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Low Latency E-Tile 40G Ethernet Design Example Registers 2.7. Design Example Interface Signals
2.5. Hardware Testing x
2.5.1. Internal Loopback Test 2.5.2. External Loopback Test
1. Quick Start Guide
2. Design Example Description
A. Low Latency E-Tile 40G Ethernet Intel FPGA IP Archives
3. Document Revision History for Low Latency E-Tile 40G Ethernet Design Example User Guide

1.5. Changing Target Device in Hardware Design Example

If you have selected Stratix 10 TX E-Tile Transceiver Signal Integrity Development Kit as your target device, the Low Latency E-Tile 40G Ethernet Intel® FPGA IP core generates a hardware example design for target device 1ST280EY2F55E2VG .

If you have selected Intel Agilex 7 F-series Transceiver-SoC Development Kit as your target device, the Low Latency E-Tile 40G Ethernet Intel® FPGA IP core generates a hardware example design for target device AGFB014R24A2E2VR0 .

The specified target device may differ from the device on your development kit.

To change the target device in your hardware design example, follow these steps:

  1. Launch the Quartus® Prime Pro Edition software and open the hardware test project file /hardware_test_design/eth_ex_40g.qpf.
  2. On the Assignments menu, click Device. The Device dialog box appears.
  3. In the Device dialog box, select an E-tile based target device table that matches the device part number on your development kit. Refer to the development kit link on the Intel® website for more information.
  4. A prompt appears when you select a device, as shown in the figure below. Select No to preserve the generated pin assignments and I/O assignments.
    Figure 5.  Quartus® Prime Prompt for Device Selection
  5. Perform full compilation of your design.
You can now test the design on your hardware.
Related Information
Level Two Title