Low Latency E-Tile 40G Ethernet Intel® FPGA IP Design Example User Guide

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ID 683747
Date 7/12/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description A. Low Latency E-Tile 40G Ethernet Intel FPGA IP Archives 3. Document Revision History for Low Latency E-Tile 40G Ethernet Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design Example 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Changing Target Device in Hardware Design Example 1.6. Testing the Low Latency E-Tile 40G Ethernet Intel® FPGA IP Design in Hardware
1.1. Generating the Design Example x
1.1.1. Design Example Parameters
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Low Latency E-Tile 40G Ethernet Design Example Registers 2.7. Design Example Interface Signals
2.5. Hardware Testing x
2.5.1. Internal Loopback Test 2.5.2. External Loopback Test
1. Quick Start Guide
2. Design Example Description
A. Low Latency E-Tile 40G Ethernet Intel FPGA IP Archives
3. Document Revision History for Low Latency E-Tile 40G Ethernet Design Example User Guide

2.3. Functional Description

This section describes the 40G Ethernet MAC/PCS IP core using the Intel device in E-tile based transceiver.

In the transmit direction, the MAC accepts client frames and inserts inter-packet gap (IPG), preamble, the start of frame delimiter (SFD), padding, and CRC bits before passing them to the PHY. The PHY encodes the MAC frame as required for reliable transmission over the media to the remote end.

In the receive direction, the PHY passes frames to the MAC. The MAC accepts frames from the PHY, performs checks, strips out the CRC, preamble, and SFD, and passes the rest of the frame to the client.

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